ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 43

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

Prescaling and
Conversion Timing
1187D–12/01
mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR
bit in ADCSR selects between the two available modes.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference
and input channel selections will not go into effect until ADEN is set. The ADC does not
consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering Power-saving sleep modes.
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be set to zero by
hardware when the conversion is completed. If a different data channel is selected while
a conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
The ADC generates a 10-bit result, which is presented in the ADC data registers, ADCH
and ADCL. By default, the result is presented right-adjusted, but can optionally be pre-
sented left-adjusted by setting the ADLAR bit in ADMUX.
If the result is left-adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the data registers belongs to the same conversion. Once ADCL is read, ADC access
to data registers is blocked. This means that if ADCL has been read, and a conversion
completes before ADCH is read, neither register is updated and the result from the con-
version is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-
enabled.
The ADC has its own interrupt, which can be triggered when a conversion completes.
When ADC access to the data registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Figure 26. ADC Prescaler
The successive approximation circuitry requires an input clock frequency between
50 kHz and 200 kHz. Using a higher input frequency will affect the conversion accuracy,
see “ADC Characteristics” on page 50. The ADC module contains a prescaler, which
divides the system clock to an acceptable ADC clock frequency.
The ADPSn bits in ADCSR are used to generate a proper ADC clock input frequency
from any CK frequency above 100 kHz. The prescaler starts counting from the moment
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
ATtiny15L
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