ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 20

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

The Timer/Counter Interrupt
Mask Register – TIMSK
20
ATtiny15L
• Bit 6 – INTF0: External Interrupt Flag0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the
MCU will jump to the interrupt vector at address $001. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1”
to it. The flag is always cleared when INT0 is configured as level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When an event on any input or I/O pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to
the interrupt vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at
vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 5..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit
$39
Read/Write
Initial Value
R
7
–
0
OCIE1A
R/W
6
0
R
5
–
0
R
4
–
0
R
3
–
0
TOIE1
R/W
2
0
TOIE0
R/W
1
0
R
0
–
0
1187D–12/01
TIMSK