ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 27

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

The 8-bit Timer/Counter0
The Timer/Counter0 Control
Register – TCCR0
1187D–12/01
Figure 20 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external
pin. In addition, it can be stopped as described in the specification for the
Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the
Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the
Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for
Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).
When Timer/Counter0 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To ensure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high-prescaling opportunities
make the Timer/Counter0 useful for lower-speed functions or exact-timing functions with
infrequent actions.
Figure 20. Timer/Counter0 Block Diagram
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
Bit
$33
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
T/C CLK SOURCE
R
4
–
0
R
3
–
0
CS02
R/W
2
0
CS01
R/W
1
0
ATtiny15L
CS00
R/W
0
0
TCCR0
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