ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 32

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

32
ATtiny15L
Table 12. Compare Mode Select in PWM Mode
Note that in PWM mode, writing to the Output Compare OCR1A, the data value is first
transferred to a temporary location. The value is latched into OCR1A when the
Timer/Counter reaches OCR1B. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR1A write. See Figure 22 for an
example.
Figure 22. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1B register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is
shown in Table 13.
COM1A1
Synchronized OC1A Latch
Unsynchronized OC1A Latch
0
0
1
1
COM1A0
0
1
0
1
Effect on Compare Pin
Not connected
Not connected
Cleared on compare match (up-counting) (non-inverted PWM). Set
when TCNT1 = $00.
Set on compare match (up-counting) (inverted PWM). Cleared when
TCNT1 = $00.
Glitch
Compare Value Changes
Compare Value Changes
Counter Value
Compare Value
PWM Output OC1A
Counter Value
Compare Value
PWM Output OC1A
1187D–12/01