ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 227

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Table 95. Boundary-scan Signals for the ADC
Note:
2570A–AVR–09/04
Signal Name
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
1. Incorrect setting of the switches in Figure 107 will make signal contention and may damage the part. There are several input
choices to the S&H circuitry on the negative input of the output comparator in Figure 107. Make sure only one path is
selected from either one ADC pin, Bandgap reference source, or Ground.
Direction as seen
from the ADC
Input
Input
Input
Input
Input
Input
Input
Input
Description
Input Mux for negative input for differential
signal, bit 2
Input Mux for negative input for differential
signal, bit 1
Input Mux for negative input for differential
signal, bit 0
Enable pass-gate of differential amplifier.
Precharge output latch of comparator.
(Active low)
Switch-cap TEST enable. Output from
differential amplifier send out to Port Pin
having ADC_4
Output of differential amplifier will settle
faster if this signal is high first two ACLK
periods after AMPEN goes high.
Selects Vcc as the ACC reference voltage.
If the ADC is not to be used during scan, the recommended input values from Table 95
should be used. The user is recommended not to use the differential amplifier during
scan. Switch-Cap based differential amplifier require fast operation and accurate timing
which is difficult to obtain when used in a scan chain. Details concerning operations of
the differential amplifier is therefore not provided.
The AVR ADC is based on the analog circuitry shown in Figure 107 with a successive
approximation algorithm implemented in the digital logic. When used in Boundary-scan,
the problem is usually to ensure that an applied analog voltage is measured within some
limits. This can easily be done without running a successive approximation algorithm:
apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-
parator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the
output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
When using the ADC, remember the following
•
•
•
The port pin for the ADC channel in use must be configured to be an input with pull-
up disabled to avoid signal contention.
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed
when enabling the ADC. The user is advised to wait at least 200ns after enabling the
ADC before controlling/observing any ADC signal, or perform a dummy conversion
before using the first result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD
signal low (Sample mode).
(1)
(Continued)
ATmega325/3250/645/6450
Recommended
Input when not
in use
0
0
0
1
0
0
0
1
Output Values when
recommended inputs are used,
and CPU is not using the ADC
0
0
0
1
1
0
0
0
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