ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 76

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

External Interrupts
External Interrupt Control
Register A – EICRA
76
ATmega325/3250/645/6450
The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins
are configured as outputs. This feature provides a way of generating a software inter-
rupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles.
Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The
PCMSK3, PCMSK2, PCMSK1, and PCMSK0 Registers control which pins contribute to
the pin change interrupts. Pin change interrupts on PCINT30..0 are detected asynchro-
nously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the External Interrupt Control Register A –
EICRA. When the INT0 interrupt is enabled and is configured as level triggered, the
interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Sys-
tems and their Distribution” on page 25. Low level interrupt on INT0 is detected
asynchronously. This implies that this interrupt can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes
except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 25.
The External Interrupt Control Register A contains control bits for interrupt sense
control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 45. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 45. Interrupt 0 Sense Control
Bit
Read/Write
Initial Value
ISC01
0
0
1
1
ISC00
R
7
–
0
0
1
0
1
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
ISC01
R/W
1
0
ISC00
R/W
0
0
2570A–AVR–09/04
EICRA