DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 231

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

Timing Requirements
Timing Specifications
Traps .................................................................................. 43
U
UART
© 2011 Microchip Technology Inc.
10-bit High-Speed A/D Conversion (CHPS = 01,
10-bit High-Speed A/D Conversion (CHPS = 01,
Input Capture ........................................................... 199
Band Gap Start-up Time Requirements ................... 195
CAN I/O Requirements ............................................ 213
CLKOUT and I/O Characteristics ............................. 193
CLKOUT and I/O Requirements .............................. 193
External Clock Requirements .................................. 189
Internal Clock Examples .......................................... 191
I
I
Motor Control PWM Requirements .......................... 201
Output Compare Requirements ............................... 199
PLL Clock ................................................................. 190
PLL Jitter .................................................................. 190
QEI External Clock Requirements ........................... 198
QEI Index Pulse Requirements ................................ 203
Quadrature Decoder Requirements ......................... 202
Reset, Watchdog Timer, Oscillator Start-up Timer,
Simple OC/PWM Mode Requirements .................... 200
SPI Master Mode (CKE = 0) Requirements ............. 204
SPI Master Mode (CKE = 1) Requirements ............. 205
SPI Slave Mode (CKE = 0) Requirements ............... 206
SPI Slave Mode (CKE = 1) Requirements ............... 207
Timer1 External Clock Requirements ...................... 196
Timer2 and Timer4 External Clock Requirements ... 197
Timer3 and Timer5 External Clock Requirements ... 197
10-bit High-Speed A/D ............................................. 214
10-bit High-Speed A/D Conversion Requirements .. 218
Hard and Soft ............................................................. 44
Sources ...................................................................... 43
Vectors ....................................................................... 44
Address Detect Mode .............................................. 124
Auto-Baud Support .................................................. 125
Baud Rate Generator (BRG) .................................... 124
Disabling .................................................................. 122
Enabling and Setup .................................................. 122
Loopback Mode ....................................................... 124
Module Overview ..................................................... 120
Operation During CPU Sleep and Idle Modes ......... 125
Receiving Data ......................................................... 123
Reception Error Handling ......................................... 123
Setting Up Data, Parity and Stop Bit Selections ...... 122
Transmitting Data ..................................................... 122
2
2
C Bus Data Requirements (Master Mode) ............ 210
C Bus Data Requirements (Slave Mode) .............. 212
SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 216
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ............................................... 217
Power-up Timer and Brown-out Reset
Requirements .................................................. 195
In 8-bit or 9-bit Data Mode ............................... 123
Interrupt ........................................................... 123
Receive Buffer (UxRXB) .................................. 123
Framing Error (FERR) ..................................... 124
Idle Status ........................................................ 124
Parity Error (PERR) ......................................... 124
Receive Break ................................................. 124
Receive Buffer Overrun Error (OERR Bit) ....... 123
In 8-bit Data Mode ........................................... 122
In 9-bit Data Mode ........................................... 122
Interrupt ........................................................... 123
dsPIC30F6010A/6015
Unit ID Locations ............................................................. 152
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ........................................................ 152
Wake-up from Sleep and Idle ............................................ 45
Watchdog Timer (WDT) ........................................... 152, 162
WWW Address ................................................................ 231
WWW, On-Line Support ...................................................... 7
UART1 Register Map .............................................. 126
UART2 Register Map .............................................. 126
Module (UART) ........................................................ 120
Enabling and Disabling ............................................ 162
Operation ................................................................. 162
Transmit Break ................................................ 123
Transmit Buffer (UxTXB) ................................. 122
DS70150E-page 231