DSPIC30F6010A MICROCHIP [Microchip Technology], DSPIC30F6010A Datasheet - Page 65

• Manufacturer Part Number: DSPIC30F6010A
• Description: High-Performance, 16-bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

9.0
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated operational
modes.
The following sections provide a detailed description,
including setup and control registers along with associ-
ated block diagrams for the operational modes of the
timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock, or operate as
a free running interval timer/counter. The 16-bit timer
has the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep modes
• Interrupt on 16-bit Period register match or falling
FIGURE 9-1:
© 2011 Microchip Technology Inc.
Note:
Note:
edge of external gate signal
TIMER1 MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Timer1 is a Type A timer. Refer to
Section 24.0 “Electrical Characteris-
tics”
SOSCO/
SOSCI
T1IF
Event Flag
T1CK
for the Type A timer specifications.
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
TGATE
0
1
Reset
Equal
LPOSCEN
Comparator x 16
TMR1
PR1
Q
Q
Gate
Sync
CK
T
D
CY
dsPIC30F6010A/6015
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON.
1
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register, PR1, then
resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous mode
of operation and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
presents a block diagram of the 16-bit timer module.
TGATE
1 x
0 1
0 0
TON
TSYNC
0
1
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
DS70150E-page 65
Figure 9-