MC9S08QD2MPS FREESCALE [Freescale Semiconductor, Inc], MC9S08QD2MPS Datasheet - Page 31
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MC9S08QD2MPS
Manufacturer Part Number
MC9S08QD2MPS
Description
8-Bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S08QD2MPS.pdf
(202 pages)
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3.6.4
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3.
LVD is enabled.
3.6.5
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode,” and
Freescale Semiconductor
1
Mode
Stop3
Mode
Stop3
ICS can be configured to run in stop3. Please see the ICS registers.
LVD Enabled in Stop Mode
On-Chip Peripheral Modules in Stop Modes
Section 3.6.2, “Stop3
PPDC
PPDC
0
0
1
CPU
RAM
Flash
Parallel Port Registers
ADC1
ICS
TPM1 & TPM2
Voltage Regulator
I/O Pins
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
CPU, Digital
Peripherals,
CPU, Digital
Peripherals,
Standby
Standby
Flash
Flash
Peripheral
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Mode,” for specific information on system behavior in stop modes.
Standby
Standby
RAM
RAM
Table 3-4. Stop Mode Behavior
Table 3-3
Active
Off
ICS
ICS
1
States Held
summarizes the behavior of the MCU in stop when the
Standby
Standby
Stop2
Off
Off
Off
Off
Off
Off
Optionally on
Optionally on
ADC1
ADC1
Mode
Regulator
Regulator
Active
Active
Optionally On
States Held
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Stop3
States held Optionally on
States held Optionally on
I/O Pins
I/O Pins
Chapter 3 Modes of Operation
Section 3.6.1, “Stop2
1
RTI
RTI
31
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