MC9S08QD2MPS FREESCALE [Freescale Semiconductor, Inc], MC9S08QD2MPS Datasheet - Page 43
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MC9S08QD2MPS
Manufacturer Part Number
MC9S08QD2MPS
Description
8-Bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S08QD2MPS.pdf
(202 pages)
- Current page: 43 of 202
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4.5.5
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be
processed.
Freescale Semiconductor
•
•
Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
Access Errors
Figure 4-3. Flash Burst Program Flowchart
MC9S08QD4 Series MCU Data Sheet, Rev. 3
YES
0
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NEW BURST COMMAND ?
TO LAUNCH COMMAND
AND CLEAR FCBEF
WRITE 1 TO FCBEF
WRITE TO FCDIV
WRITE TO FLASH
CLEAR ERROR
FACCERR ?
FACCERR ?
FPVIO OR
FCBEF ?
FCCF ?
START
DONE
1
NO
NO
1
1
(1)
(2)
0
0
YES
(2)
Chapter 4 Memory Map and Register Definition
checking FCBEF or FCCF.
(1)
Wait at least four bus cycles before
after reset.
Required only once
ERROR EXIT
43
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