MC9S08QD2MPS FREESCALE [Freescale Semiconductor, Inc], MC9S08QD2MPS Datasheet - Page 67

• Manufacturer Part Number: MC9S08QD2MPS
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2
5.8.9
This high-page register contains status and control bits to configure the stop mode behavior of the MCU.
See
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
LVWF will be set in the case when V
LVDR:
Reset
Other
LVDRE
LVDSE
POR:
LVDIE
BGBE
LVDE
Field
Section 3.6, “Stop
5
4
3
2
0
W
R
LVWF
System Power Management Status and Control 2 Register
(SPMSC2)
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
0
0
0
7
2
2
2
= Unimplemented or Reserved
LVWACK
Table 5-12. SPMSC1 Register Field Descriptions (continued)
Modes,” for more information on stop modes.
0
0
0
0
6
supply
MC9S08QD4 Series MCU Data Sheet, Rev. 3
LVDV
transitions below the trip point or after reset and V
U
U
0
5
LVWV
U
U
0
4
Description
Chapter 5 Resets, Interrupts, and General System Control
PPDF
3
0
0
0
PPDACK
U = Unaffected by reset
0
0
0
0
2
supply
is already below V
0
0
0
1
PPDC
LVW
0
0
0
0
.
1
67