ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 13
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ISPPACCLK5316S-01T48C
Manufacturer Part Number
ISPPACCLK5316S-01T48C
Description
In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.ISPPACCLK5316S-01T48C.pdf
(56 pages)
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- Download datasheet (2Mb)
Lattice Semiconductor
Static Phase Offset vs. Reference Clock Logic Type
Boundary Scan Logic
t
1. The output clock to feedback can be skewed to center the static phase offset spread.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(
BTCP
BTCH
BTCL
BTSU
BTH
BRF
BTCO
BTOZ
BTVO
BVTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
φ
)
– Static Phase Offset
Symbol
Symbol
TCK (BSCAN Test) Clock Cycle
TCK (BSCAN Test) Pulse Width High
TCK (BSCAN Test) Pulse Width Low
TCK (BSCAN Test) Setup Time
TCK (BSCAN Test) Hold Time
TCK (BSCAN Test) Rise and Fall Rate
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Data Output Disable
TAP Controller Falling Edge of Clock to Data Output Enable
BSCAN Test Capture Register Setup Time
BSCAN Test Capture Register Hold Time
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
BSCAN Test Update Register, Falling Edge of Clock to Output Disable
BSCAN Test Update Register, Falling Edge of Clock to Output Enable
LVCMOS 33
LVCMOS 25
LVCMOS 18
SSTL3
SSTL2
HSTL(1.5V)
eHSTL(1.8V)
LVDS (2.5V)
LVPECL
Reference Clock Logic
(REFA/REFB)
1
1
Parameter
LVCMOS33
LVCMOS25
LVCMOS18
SSTL3
SSTL2
HSTL(1.5V)
eHSTL(1.8V)
LVDS-Single Ended
LVPECL-Single Ended LVCMOS33
Feedback Input
Logic (FBK)
13
LVCMOS33
LVCMOS25
LVCMOS18
SSTL3
SSTL2
HSTL(1.5V)
eHSTL(1.8V)
LVCMOS25
Feedback Output Logic
(BANK_xA/BANK_xB)
ispClock5300S Family Data Sheet
Min.
40
20
20
10
50
10
—
—
—
—
—
—
8
8
Min.
-100
-100
140
-40
-70
-80
-70
-70
80
Max.
10
10
10
25
25
25
—
—
—
—
—
—
—
—
Max.
100
390
340
360
360
530
300
80
80
mV/ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
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