ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 37

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 32. ispClock5300S TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 33. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
TDI
(42 Bits for ispClock5312S, 5308S 5304S,
(34 Bits for ispClock5312S, 5308S, 5304S,
61 Bits for ispClock5320S and 5316S)
Test Acess Port (TAP)
50 Bits for ispClock5320S and 5316S)
TCK
Instruction Register (8 Bits)
IDCODE Register (32 Bits)
Address Register (10 Bits)
Boundary Scan Register
Bypass Register (1 Bit)
UES Register (32 Bits)
Logic
Data Register
TMS
37
Output
Latch
TDO
ispClock5300S Family Data Sheet
Non-Volatile
E
Memory
2
CMOS