ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 26

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 21. Configuration for SSTL2, SSTL3, and HSTL Output Modes
ispClock5300S Configurations
The ispClock5300S device can be configured to operate in four modes. They are:
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•
•
•
The output routing matrix of the ispClock5300S provides up to three independent any-to-any paths from inputs to
outputs:
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•
•
Zero Delay Buffer Mode
Figure 22 shows the ispClock5300S device configured to operate in the Zero Delay Buffer mode. The Clock input
can be single ended or differential. Two single ended clocks can be selected by the use of REFSEL pin and if the
input is configured as a differential the REFSEL pin should be connected to GNDD. The input clock then drives the
Phase frequency detector of the PLL. Up to 3 output clock frequencies can be generated from the input reference
clock by the use of V-dividers at the output of PLL. Any V-divider output can be connected to any of the output pins.
However, one of the V-dividers should be used in the feedback path to set the PLL operating frequency. The PLL
can operate with internal or external feedback path.
In this mode, the skew control mechanism is active for all outputs.
Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Non-Zero Delay Buffer mode 1
Non-Zero Delay Buffer Mode 2
From any V-Dividers to any output in ZDB mode or PLL Bypass modes
From selected clock via REFSEL pin to any output (note single ended reference clock)
From the other clock not selected by REFSEL pin to any output
Ro : 40 (SSTL)
SSTL/HSTL/eHSTL
Mode
20 (HSTL, eHSTL)
ispClock5300S
26
Zo=50
ispClock5300S Family Data Sheet
VREF
RT=50
VTT
SSTL/HSTL/eHSTL
Receiver