ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 24

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5300S’s ability to adjust input impedance over a range of
40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5300S provides multiple banks, with each bank supporting two high-speed clock outputs which are
configurable and internally terminated. There are ten banks in the ispClock5320S, eight banks in the
ispClock5316S, six banks in the ispClock5312S, four banks in the ispClock5308S and two banks in the
ispClock5304S. Programmable internal source-series termination allows the ispClock5300S to be matched to
transmission lines with impedances ranging from 40 to 70Ω. The outputs may be independently enabled or dis-
abled, either from E
grammed to provide a fixed amount of signal delay or skew, allowing the user to compensate for the effects of
unequal PCB trace lengths or loading effects. Figure 19 shows a block diagram of a typical ispClock5300S output
driver bank and associated skew control.
Because of the high edge rates which can be generated by the ispClock5300S clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 µF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDO pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 19. ispClock5300S Output Driver and Skew Control
*Skew Adjust Mechanism is applicable only to outputs connected to one of the three V-Dividers and
when PLL is active (PLL-Bypass pin = 0). For all other conditions, Skew Adjust Mechanism is bypassed.
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CMOS configuration or by external control lines. Additionally, each can be independently pro-
V-Dividers
V-Dividers
From
From
Adjust*
Adjust*
Skew
Skew
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OE Control
OE Control
ispClock5300S Family Data Sheet
Output A Driver
Output B Driver
Single Ended
Single Ended
VCCO-x
Bank_xA
Bank_xB
GNDO-x