ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 56

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
October 2006
October 2007
June 2006
April 2006
May 2006
Date
[phone] (Outside North America)
[e-mail]
Version
01.0
01.1
01.2
01.3
01.4
Initial release.
Performance Characteristics-PLL table - Correction to min. output frequency, f
Skew Mode. Min frequency = 5MHz.
Programmable Skew table - Correction to number of skew steps (from 16 to 8).
Programmable Skew table - Correction to Skew control range.
Output V Dividers section - Added explanation to V-divider settings as Power of 2 Settings
(1, 2, 4, 8, 16, 32).
Added Reset Signal Slew Rate specification to Control Functions table.
Modified pin descriptions in Pin Descriptions table to reflect changes to pin 48 from NC to
GNDD.
Modified package diagrams to reflect the pin 48 changes from NC to GNDD.
Modified RESET pin description to include pull-up resistor when not driven.
Included references to ispClock5316S and ispClock5320S devices.
Added typical performance graphs.
Updated Boundary Scan Register information in ispClock5300S TAP Registers diagram.
Added support for the Internal Feedback mode of operation.
56
Change Summary
ispClock5300S Family Data Sheet
OUT
in Fine