FDD8880_08 FAIRCHILD [Fairchild Semiconductor], FDD8880_08 Datasheet - Page 8

• Manufacturer Part Number: FDD8880_08
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

©2008 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT FDD8880 2 1 3 ; rev April 2004
Ca 12 8 9.5e-10
Cb 15 14 9.5e-10
Cin 6 8 1.15e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.15
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.3e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.7e-9
RLgate 1 9 53
RLdrain 2 5 10
RLsource 3 7 17
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.2e-3
Rgate 9 20 2.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}
.MODEL DbodyMOD D (IS=2E-12 IKF=10 N=1.01 RS=3.76e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=4.8e-10 M=0.55 TT=1e-17 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=2.0 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2)
.MODEL MstroMOD NMOS (VTO=2.5 KP=170 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.69 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=1.8e-3 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1e-3 TC2=-8.2e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.3 VOFF=-0.8)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
RSLC2
6
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
+
-
MSTRO
14
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
MWEAK
17
RVTHRES
RBREAK
11
+
-
17
18
7
+
18
-
22
RVTEMP
19
RLSOURCE
DBODY
LSOURCE
VBAT
RLDRAIN
LDRAIN
FDD8880 Rev. B3
SOURCE
DRAIN
2
3