A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 10

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3E Device Family Overview
Part Number and Revision Date
List of Changes
1 -6
Previous Version
51700098-001-1
51700098-001-0
(January 2008)
v2.1
(July 2007)
v2.0
(April 2007)
Advance v0.6
(January 2007)
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages
(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-
ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks
per device (two per side). The configuration of these banks determines the I/O standards
supported. Each I/O bank is subdivided into V
I/Os. V
Therefore, if any I/O in a given V
minibank will be able to use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Part Number 51700098-001-1
Revised March 2008
The following table lists critical changes that were made in the current version of the document.
•
•
REF
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
The FG324 package was added to the
"I/Os Per Package1"
A3PE3000.
This document was previously in datasheet v2.1. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700098-001-0.
CoreMP7 information was removed from the "Features and Benefits" section.
The M1 device part numbers have been updated in Table 4 • ProASIC3E
Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed
Grade and Temperature Grade Matrix", and "Speed Grade and Temperature
Grade Matrix".
The words "ambient temperature" were added to the temperature range in
the "Temperature Grade Offerings", "Speed Grade and Temperature Grade
Matrix", and "Speed Grade and Temperature Grade Matrix" sections.
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
In the "Temperature Grade Offerings" section, Ambient was deleted.
Ambient was deleted from "Temperature Grade Offerings".
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
This document was divided into two sections and given a version number,
minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common V
table, and the
Changes in Current Version (v1.0)
REF
minibank is configured as a V
v1.0
"Temperature Grade Offerings"
REF
"ProASIC3E Product Family"
minibanks, which are used by voltage-referenced
REF
pin, the remaining I/Os in that
table, the
table for
iii, ii, iii,
iii, iv, iv
I, II,
REF
Page
iv, iv
N/A
N/A
iii
iii
iv
i
i
line.
IV