A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 77

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Global Resource Characteristics
Figure 2-37 • Example of Global Tree Use in an A3PE600 Device for Clock Routing
CCC
A3PE600 Clock Tree Topology
Clock delays are device-specific.
The global tree presented in
device. It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
capabilities, refer to the
page
global clock delays within the device. Minimum and maximum delays are measured with minimum
and maximum loading.
2-66,
Table 2-92 on page
"Clock Conditioning Circuits" section on page
Figure 2-37
2-66, and
Figure 2-37
is driven by a CCC located on the west side of the A3PE600
v1.2
Table 2-93 on page 2-67
is an example of a global tree used for clock routing.
ProASIC3E DC and Switching Characteristics
present minimum and maximum
2-68.
Table 2-91 on
Central
Global Rib
VersaTile
Rows
Global Spine
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