A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 22

• Manufacturer Part Number: A3PE1500-1FG896
• Description: ProASIC3E Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3E DC and Switching Characteristics
2 -1 0
1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated
by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include
each output clock in the formula by adding its corresponding contribution (P
contribution.
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
P
P
P
P
P
C-CELL
NET
INPUTS
OUTPUTS
MEMORY
PLL
= (N
= P
N
α
page 2-11
F
N
N
α
page 2-11
F
N
α
F
N
α
β
F
N
F
β
on page 2-11
F
β
on page 2-11
F
CLK
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
1
2
3
C-CELL
S-CELL
C-CELL
= N
INPUTS
OUTPUTS
BLOCKS
1
1
2
2
= N
AC13
is the I/O buffer enable rate—guidelines are provided in
S-CELL
is the RAM enable rate for read operations—guidelines are provided in
is the RAM enable rate for write operations—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
= N
is the I/O buffer toggle rate—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
= P
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
INPUTS
C-CELL
AC11
OUTPUTS
+ P
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
+ N
is the output clock frequency.
is the number of RAM blocks used in the design.
.
.
AC14
is the number of I/O output buffers used in the design.
*
*
* N
C-CELL
α
α
is the memory read clock frequency.
.
.
is the memory write clock frequency.
PLL
*
1
2
BLOCKS
* F
MEMORY
/ 2 * P
/ 2 * P
α
) *
CLKOUT
2
/ 2 *
α
* F
AC7
AC9
1
NET
/ 2 * P
READ-CLOCK
β
* F
* F
1
* P
INPUTS
CLK
CLK
AC8
OUTPUTS
AC10
C-CELL
v1.2
* F
*
* F
CLK
β
CLK
2
+ P
1
AC12
* N
BLOCK
AC14
* F
* F
WRITE-CLOCK
CLKOUT
Table 2-11 on page 2-11
Table 2-11 on page 2-11
Table 2-12 on page 2-11
product) to the total PLL
*
β
3
Table 2-11 on
Table 2-11 on
Table 2-12
Table 2-12
.
.
.