A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 69

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A3PE1500-1FG896

Manufacturer Part Number
A3PE1500-1FG896
Description
ProASIC3E Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Figure 2-29 • Input DDR Timing Model
Table 2-85 • Parameter Definitions
Parameter Name
t
t
t
t
t
t
t
t
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
CLK
Data
CLR
DDR Module Specifications
Input DDR Module
INBUF
CLKBUF
INBUF
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
B
C
A
Parameter Definition
Input DDR
v1.2
DDR_IN
ProASIC3E DC and Switching Characteristics
FF1
FF2
Measuring Nodes (from, to)
D
E
B, D
A, B
A, B
C, D
C, E
C, B
C, B
B, E
Out_QF
(to core)
Out_QR
(to core)
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