A3PE1500-1FG896 ACTEL [Actel Corporation], A3PE1500-1FG896 Datasheet - Page 70

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A3PE1500-1FG896

Manufacturer Part Number
A3PE1500-1FG896
Description
ProASIC3E Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
ProASIC3E DC and Switching Characteristics
Figure 2-30 • Input DDR Timing Diagram
Table 2-86 • Input DDR Propagation Delays
2 -5 8
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
DDRICLKQ1
Description
J
= 70°C, Worst-Case V
4
2
v1.2
3
5
CC
t
DDRICLKQ2
t
= 1.425 V
DDRISUD
6
4
Table 2-6 on page 2-5
5
1404 1232 1048
0.39
0.00
0.22
0.22
0.36
0.32
0.27
0.28
0.57
0.46
0.00
–2
7
0.44
0.31
0.32
0.00
0.65
0.53
0.00
0.25
0.25
0.41
0.37
–1
t
DDRIHD
t
8
DDRIRECCLR
6
0.52
0.37
0.38
0.00
0.76
0.62
0.00
0.30
0.30
0.48
0.43
Std.
7
for derating
0.62
0.44
0.45
0.00
0.92
0.74
0.00
0.36
0.36
0.57
0.52
871
–F
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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