HV51V7403HGL-5 Hynix Semiconductor, HV51V7403HGL-5 Datasheet - Page 4
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HV51V7403HGL-5
Manufacturer Part Number
HV51V7403HGL-5
Description
4M x 4Bit EDO DRAM
Manufacturer
Hynix Semiconductor
Datasheet
1.HV51V7403HGL-5.pdf
(11 pages)
DC CHARACTERISTICS
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while /RAS=VIL
3. Address can be changed once or less while /CAS=VIH
4. /CAS = L (<=0.2) while /RAS=L (<=0.2)
5. L-Version
Symbol
Rev.0.1/Apr.01
ICC5
ICC7
ICC8
ICC9
IO(L)
VOH
VOL
ICC1
I
ICC3
ICC4
ICC6
II(L)
CC2
Output Level
Output Level voltage(Iout= -2mA)
Output Level
Output Level voltage(Iout=2mA)
Operating current
Average power supply operating current
( /RAS, /CAS Cycling : tRC = tRC min)
Standby current (TTL interface)
Power supply standby current
(/RAS, /CAS=VIH, Dout = High-Z)
/RAS only refresh current
Average power supply current
/RAS only refresh mode
(tRC= tRC min)
Fast page mode current
Average power supply current
Fast page mode (tPC=tPC min)
CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z)
Standby current ( L-version)
/CAS-before-/RAS refresh current (tRC=tRC min)
Battery back up operating current (standby with CBR refresh)
(tRC=31.3us, tRAS<=0.3us, Dout=High-Z)
Standby current
( /RAS = VIH, /CAS = VIL, Dout=Enable)
Self refresh current
(/RAS, /CAS <=0.2V, Dout=High-Z, CMOS interface)
Input leakage current, Any input (0V<= Vin<=4.6V)
Output leakage current, (Dout is disabled, 0V<= Vout<=4.6V)
(Vcc = 3.3V +/- 10%, TA=0 to 70 C)
Parameter
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
HY51V(S)17403HG/HGL
Min
2.4
-10
-10
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
Vcc
100
100
100
100
300
200
0.4
90
80
90
80
90
80
75
90
80
10
10
2
1
5
Unit
mA
mA
mA
mA
mA
mA
uA
uA
uA
uA
uA
uA
V
V
Note
1, 2
1, 3
4
4
1
4
2
4