LRS1341 Sharp, LRS1341 Datasheet - Page 19

• Manufacturer Part Number: LRS1341
• Description: Stacked Chip 16M Flash Memory and 2M SRAM
• Manufacturer: Sharp

Stacked Chip (16M Flash & 2M SRAM)
Data Sheet
1. A write occurs during the overlap of a LOW S-CE
2. t
3. t
4. t
5. t
6. During this period, DQ pins are in the output state, therefore the input signals of
7. If S-CE
NOTES:
and S-WE going LOW. A write ends at the earliest transition among S-CE
S-CE
write to the end of write.
opposite phase to the outputs must not be applied.
A write begins at the latest transition among S-CE
of write.
after S-WE going LOW, the outputs remain in HIGH impedance state.
CW
BW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the later of S-CE
is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
is measured from the end of write to the address change.
2
S-UB, S-LB
ADDRESS
going LOW and S-WE going HIGH. t
1
goes LOW or S-CE
S-CE
S-CE
S-WE
D
D
OUT
IN
1
2
2
Figure 11. Write Cycle Timing Diagram (S-CE Controlled)
goes HIGH simultaneously with S-WE going LOW or
1
(NOTE 4)
going LOW or S-CE
t
WP
AS
is measured from the beginning of
1
, a HIGH S-CE
1
going LOW, S-CE
2
going HIGH to the end
HIGH IMPEDANCE
2
t
and a LOW S-WE.
AW
(NOTE 7)
(NOTE 6)
2
t
WP
going HIGH
t
WC
1
(NOTE 2)
(NOTE 3)
going HIGH,
t
t
CW
BW
t
DW
Data Valid
(NOTE 5)
t
t
WR
WR
t
DH
LRS1341/LRS1342
LRS1342-10
19