LRS1341 Sharp, LRS1341 Datasheet - Page 4

• Manufacturer Part Number: LRS1341
• Description: Stacked Chip 16M Flash Memory and 2M SRAM
• Manufacturer: Sharp

LRS1341/LRS1342
NOTES:
1. L = V
2. Refer to the ‘Flash Memory Command Definition’ section for valid
3. F-WP set to V
4. SRAM standby mode. See Table 2a.
NOTES:
1. Commands other than those shown in table are reserved by
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
4
Read
Output Disable
Write
Standby
Reset/Power Down
Standby
Reset/Power Down Standby
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and Word
Write Suspend
Block Erase and Word
Write Resume
D
SHARP for future device implementations and should not be used.
IA = Identifier code address;
BA = Address within the block being erased;
IN
Standby
(SRAM)
MODE
FLASH
during a write operation.
COMMAND
IL
, H = V
IH
IL
, X = H or L. Refer to DC Characteristics.
or V
S-CE
H
X
X
Standby
Standby
Standby
Read
Output
Disable
Write
Read
Output
Disable
Write
Standby
SRAM
IH
.
1
BUS CYCLES
REQUIRED
Table 2a.
S-CE
F-CE F-RP
≥ 2
H
H
H
H
H
X
X
1
2
1
2
1
1
L
L
L
X
X
X
X
X
L
2
2
Table 3. Command Definition for Flash Memory
PINS
H
H
H
H
H
H
H
H
L
L
L
L
L
OPERATION
S-LB
X
X
H
F-OE
H
H
X
X
X
X
X
X
X
X
X
X
Write
Write
Write
Write
Write
Write
Write
Write
L
F-WE
Table 2. Truth Table
FIRST BUS CYCLE
H
H
X
X
X
X
X
X
X
X
X
X
L
S-UB
2
H
X
X
ADDRESS
S-CE
See Note 4
See Note 4
L
L
L
L
L
L
L
L
WA
XA
XA
XA
XA
XA
XA
BA
1
S-CE
3
5. Command writes involving block erase or word write are reliably
6. Never hold F-OE LOW and F-WE LOW at the same time.
7. S-LB, S-UB control mode. See Table 2b.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
H
H
H
H
H
H
H
H
40H or 10H
executed when F-V
erase or word write with V
and should not be attempted.
WA = Address of memory location to be written;
SRD = Data read from status register, see Table 6;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE or F-CE (whichever goes high first);
ID = Data read from identifier codes.
2
Read/Write
DATA
(SRAM)
MODE
FFH
B0H
D0H
90H
70H
50H
20H
S-OE S-WE S-LB
1
X
X
X
H
X
H
X
X
X
L
L
L
L
3
Stacked Chip (16M Flash & 2M SRAM)
H
H
H
H
X
X
X
X
X
X
X
OPERATION
L
L
S-LB
H
L
L
Read
Read
Write
Write
PP
See Note 4
See Note 4
X
H
X
H
SECOND BUS CYCLE
= V
1
IH
PPH
Table 2b.
S-UB
2
< RP < V
S-UB
See Note 7
See Note 7
See Note 7
X
H
X
H
H
L
L
and F-V
ADDRESS
WA
DQ
DQ-7
XA
BA
IA
PINS
HH
DQ
CC
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
D
D
0
HIGH-Z
D
produce spurious results
-
OUT
OUT
D
OUT
0
= 2.7 V to 3.6 V. Block
3
IN
- DQ
DQ
DQ
/D
/D
DATA
IN
IN
8
15
SRD
D0H
WD
7
-
ID
Data Sheet
DQ
3
D
D
2, 3, 5, 6
NOTES
HIGH-Z
OUT
OUT
8
2, 3
NOTES
3
3
3
- DQ
/D
/D
4
5
5
5
5
IN
IN
15