LRS1341 Sharp, LRS1341 Datasheet - Page 22

• Manufacturer Part Number: LRS1341
• Description: Stacked Chip 16M Flash Memory and 2M SRAM
• Manufacturer: Sharp

LRS1341/LRS1342
GENERAL DESIGN GUIDELINES
Supply Power
the voltage is less than 0.3 V.
Power Supply and Chip Enable of Flash
Memory and SRAM
HIGH when F-CE is LOW simultaneously.
not operate normally because of interference noises or
data collision on DQ bus.
recommended supply voltage at the same time except
SRAM data retention mode.
Power Up Sequence
F-RP LOW. After F-V
LOW for more than 100 ns.
Device Decoupling
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE
FLASH MEMORY DATA PROTECTION
the specification may be generated under specific
operating conditions on some systems.
power supply may be interpreted as false commands,
causing undesired memory updating.
against unwanted overwriting, systems operating with
the flash memory should have the following write pro-
tect designs, as appropriate:
Protecting Data in Specific Block
be protected against overwriting. Parameter and main
blocks cannot be locked. System program, etc., can be
locked by storing them in the boot block. When a high
voltage is applied to F-RP, overwrite operation is
enabled for all blocks.
bit, and controlling of F-WP and F-RP, refer to the
‘Command Definitions’ section.
22
Maximum difference (between F-V
S-CE
If the two memories are active together, they may
Both F-V
When turning on Flash memory power supply, keep
The power supply needs to be designed carefully
Noises having a level exceeding the limit specified in
Such noises, when induced onto F-WE signal or
To protect the data stored in the flash memory
By setting a F-WP to LOW, only the boot block can
For further information on setting/resetting of block
1
should not be LOW and S-CE
CC
and S-V
CC
CC
reaches over 2.7 V, keep F-RP
need to be applied by the
CC
2
and S-V
should not be
1
, S-CE
CC
2
) of
).
Data Protection Through F-V
out voltage), write operation on the flash memory is dis-
abled. All blocks are locked and the data in the blocks
are completely write protected.
tics’ section.
Data Protection During Voltage Transition
DATA PROTECTION THROUGH F-RP
power down sequence, write operation on the flash
memory is disabled, write protecting all blocks.
Memory AC Electrical Characteristics’ section.
DESIGN CONSIDERATIONS
Power Supply Decoupling
power switching characteristics, each device should
have a 0.1 µF ceramic capacitor connected between its
V
inductance capacitors should be placed as close as
possible to package leads.
V
that reside in the target system requires that the printed
circuit board designer pay attention to the V
Supply trace. Use similar trace widths and layout con-
siderations given to the V
The Inhibition of Overwrite Operation
which has already been programmed ‘0’. Overwrite
operation may generate unerasable bit. In case of
reprogramming ‘0’ to the data which has been pro-
grammed ‘1’.
• Program ‘0’ for the bit in which you want to change
• Program ‘1’ for the bit which has already been pro-
‘1011110110111101’ to ‘1010110110111100’ requires
‘1110111111111110’ programming.
Power Supply
configuration with an invalid V
tics’) produce spurious results and should not be
attempted. Device operations at invalid V
product spurious results and should be attempted.
CC
PP
data from ‘1’ to ‘0’.
grammed ‘0’.
When the level of F-V
For the lockout voltage refer to the ‘DC Characteris-
When the F-RP is kept LOW during power up and
For details of F-RP control refer to the ‘Flash
To avoid a bad effect on the system by flash memory
Updating the memory contents of flash memories
Please do not execute reprogramming ‘0’ for the bit
F o r
Block erase, full chip erase, word write and lock-bit
and GND and between its V
Trace on Printed Circuit Boards
e x a m p l e ,
Stacked Chip (16M Flash & 2M SRAM)
PP
c h a n g i n g
CC
is lower than F-V
power bus.
PP
(see ‘DC Characteris-
PP
PP
and GND. LOW
d a t a
Data Sheet
CC
PPLK
PP
voltage
Power
(lock-
f r o m