THNCFxxxMAA Toshiba, THNCFxxxMAA Datasheet
THNCFxxxMAA
Related parts for THNCFxxxMAA
THNCFxxxMAA Summary of contents
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... No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. ｘｘｘMAA Series ｘｘｘ ｘｘｘ CompactFlash™ Card Preliminary version THNCFxxxMAA Series 2001-09-05 1/52 ...
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... THNCFxxxMAA Series Head Sector 2 32 THNCF008MAA 4 32 THNCF016MAA 4 32 THNCF032MAA 4 32 THNCF048MAA 4 32 THNCF064MAA 8 32 THNCF096MAA 8 32 THNCF128MAA ...
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... Read mode 30 mA (typ) Write mode 30 mA (typ) Sleep mode 100uA (typ) Environment conditions Environment conditions Environment conditions Environment conditions： ： ： ： Operating temperature Storage temperature Relative humidity 0℃ to 60℃ -20℃ to 65℃ 95%(Max) Preliminary version THNCFxxxMAA Series 2001-09-05 3/52 ...
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... UNIT - ℃ ℃ MIN MAX 3.0 5.5 2.2 Vcc+0.3 -0.3 * 0.8 to 65℃ ℃ ℃ ℃ , Vcc = 3.15V to 5.5V Vcc = 3.15V to 5.5V) , Vcc = 3.15V to 5.5V) , Vcc = 3.15V to 5.5V) MIN TYP 26 75 2.4 Preliminary version THNCFxxxMAA Series UNIT MAX UNIT 50 mA 200 uA V 0.4 V 2001-09-05 4/52 ...
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... TOP 42.80mm±.10) (1.685 in. ±. 004) Preliminary version THNCFxxxMAA Series 2.44mm±.07 (.096 in.±. 003) 2.15mm±.07 (.085 in. ±. 003) 2X 3.00mm ±.07 (2X .118 in. ±. 003) 0.76mm ±.07 (0.30 in. ±. 003) 0.63mm ± ...
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... PC Card Memory mode 2) PC Card I/O mode 3) True IDE mode True IDE mode is required for CompactFlash Storage cards. All outputs from the card are totem pole except the data bus signals that are bi-directional tri-state. Preliminary version THNCFxxxMAA Series 2001-09-05 6/52 ...
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... D15 I/O I1Z,OZ3 1 32 -CE2 I I3U 33 -VS1 O Ground 34 -IORD I I3U 35 -IOWR I I3U 36 -WE I I3U Preliminary version THNCFxxxMAA Series True IDE Mode Pin Signal Pin In,Out Num. Name Type Type 1 GND Ground 2 D03 I/O I1Z, OZ3 3 D04 I/O I1Z, OZ3 4 D05 I/O I1Z, OZ3 5 D06 ...
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... I3U 45 -SPKR I/O I1U,OT1 46 -STSCHG I/O I1U,OT1 1 47 D08 I/O I1Z,OZ3 1 48 D09 I/O I1Z,OZ3 1 49 D10 I/O I1Z,OZ3 50 GND Ground Preliminary version THNCFxxxMAA Series True IDE Mode Pin Signal Pin Num. Name Type 37 INTRQ O 38 VCC I2Z 39 -CSEL I 40 -VS2 O I2Z 41 -RESET I 42 IORDY O 43 ...
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... This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode CS0 is the chip select for the task file registers while CS2 is used to select the Alternate Status Register and the Device Control Register. Preliminary version THNCFxxxMAA Series Description They are used by the 2001-09-05 9/52 ...
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... CompactFlash Strage Card or CF+Card controller registers when the CompactFlash Storage Card or CF+Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal(trailing edge). In True IDE Mode, this signal has the same function Card I/O Mode. Preliminary version THNCFxxxMAA Series Description 2001-09-05 10/52 ...
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... This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode this input pin is the active low hardware reset from the host. 13,38 +5V, +3.3V power This signal is the same for all modes. This signal is the same for all modes. Preliminary version THNCFxxxMAA Series Description operation, this signal is used 2001-09-05 11/52 ...
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... I/O Operation Pin 24 is used for the –I/O Selected is 16Bit Port (-IOIS16) function. A Low signal indicates that a 16bit or odd byte only operation can be performed at the addressed port. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. Preliminary version THNCFxxxMAA Series 2001-09-05 12/52 ...
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... Dout Preliminary version THNCFxxxMAA Series D8 to D15 D8 to D15 D15 D8 to D15 High-Z High-Z H High-Z even byte H High-Z invalid H invalid even byte H invalid High-Z ...
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... Dout Preliminary version THNCFxxxMAA Series D15 D15 D8 to D15 D8 to D15 High-Z High High-Z even byte H H High-Z ...
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... Dout Preliminary version THNCFxxxMAA Series IOWR D8 to D15 IOWR IOWR D8 to D15 D8 to D15 D8 to D15 High-Z High High-Z even byte H H High-Z ...
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... OWR OWR OWR OWR 1-7H H Dout Preliminary version THNCFxxxMAA Series D8 to D15 D8 to D15 D8 to D15 D8 to D15 High-Z High-Z x High-Z High-Z H odd byte even byte H High-Z status out ...
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... Mapping mode Mapping mode Mapping mode Mapping mode 0H to FH, 400H to 7FFH Memory mapped xx0H to xxFH contiguous I/O mapped 1F0H to 1F7H,3F6H to 3F7H primary I/O mapped 1F0H to 177H,376H to 3F7H Secondary I/O mapped Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 bit bit0 bit bit 2001-09-05 17/52 ...
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... If the –IEN bit in the Device Control Register disables interrupts, this bit is a zero. Address 202H) Address 202H) Address 202H) bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 0 0 PWD Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 bit0 bit0 bit0 bit0 INTR 0 2001-09-05 18/52 ...
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... DRV Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 bit0 bit0 bit0 bit0 RRDY/-BSY 0 bit1 bit1 bit0 bit0 bit1 bit1 bit0 bit0 0 0 2001-09-05 19/52 ...
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... Specific Strings) 04AH xxh ' ' (Vender Specific Strings) 04CH xxh ' ' (Vender Specific Strings) manufacture’s JEDEC ID Preliminary version THNCFxxxMAA Series CIS function CIS function CIS function CIS function Tuple code Tuple link Tuple data Tuple data End of Tuple Tuple code ...
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... Feature Select 0A0H 01h Vcc Selection Byte 0A2H 55h Nom V Paramete 0A4H 08h Memory length (256 byte pages) Preliminary version THNCFxxxMAA Series Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data ...
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... Base address 0F8H 07h Address length 0FAH f6h Base address 0FCH 03h Base address Preliminary version THNCFxxxMAA Series Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code ...
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... Peak I Parameter 146H 14h CISTPL_NO_LINK 148H 00h TPL_LINK 14AH ffh CISTPL_END Preliminary version THNCFxxxMAA Series Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code ...
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... EH Alt. status register 1 FH Drive address register 0 8H Even data register 1 9H Odd data register Preliminary version THNCFxxxMAA Series - - - - WE=L WE=L WE=L WE=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup ...
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... Drive head register 1 1 Status register 1 0 Alt. status register 1 1 Drive address register Preliminary version THNCFxxxMAA Series - - - - IOWR=L IOWR=L IOWR=L IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup ...
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... Sector number register Sector number register Cylinder low register Cylinder low register Cylinder high register Cylinder high register Drive head register Drive head register Status register Command register Alt. status register Device control register Drive address register Reserved Preliminary version THNCFxxxMAA Series 2001-09-05 26/52 ...
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... Feature byte bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 Sector count byte Preliminary version THNCFxxxMAA Series bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit1 bit1 bit1 bit1 bit0 bit0 bit0 bit0 bit1 ...
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... Slave(Card 1) in Master/Slave organization. The card is set to be Card using DRV# of the Socket and Copy register. This bit is used for selecting the Head number for the following command. Bit 3 is MSB. Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 bit0 ...
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... This bit is always set to “0”. This bit is set when the previous command has ended in some type of error. The error information is set in this error register or other Status registers. This bit is cleared by the next command. Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 ...
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... E8H Write long sector 32H or 33H Write multiple C5H Write multiple w/o erase CDH Write sector 30H or 31H Write sector w/o erase 38H Write verify 3CH Preliminary version THNCFxxxMAA Series Used parameter Used parameter Used parameter Used parameter ...
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... Function Function Function Function This bit is unknown. This bit is unknown. These bits is the negative value of Head Select bits(bit 3 to 0)in Drive/Head register. This bit is unknown. This bit is unknown. Preliminary version THNCFxxxMAA Series bit1 bit1 bit1 bit1 bit0 bit0 bit0 bit0 nIEN 0 bit1 ...
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... Write buffer E8H 25 Write long sector 32H or 33H 26 Write multiple C5H 27 Write multiple w/o erase CDH 28 Write sector 30H or 31H 29 Write sector w/o erase 38H 30 Write verify 3CH Preliminary version THNCFxxxMAA Series ...
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... FFH or 00H). To remain host backward compatible, the card expects one sector (512Bytes) of data from the host to follow the command with same protocol as the Write Sector Command. 5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the Card. (00H to FFH) Preliminary version THNCFxxxMAA Series 2001-09-05 33/52 ...
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... Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track and the number of heads per cylinder. 9. Read Buffer (code: E4H): This command enables the host to read the current contents of the card’s sector buffer. THNCFxxxMAA Series Data field type information Data field type information Data field type information ...
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... ATA “Standby” Mode), clear BSY and return the interrupt immediately. 22. Translate Sector (code: 87H): This command allows the host a method of determining the exact number of times a use sector has been erased and programmed. Preliminary version THNCFxxxMAA Series 2001-09-05 35/52 ...
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... Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. 30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. Preliminary version THNCFxxxMAA Series The transfer begins at the sector 2001-09-05 36/52 ...
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... Read 256 times the data register (512 bytes) error handle Get all data? Wait the command input Start (1)Set the logical sector number (2)set read sector command (3)Polling until ready “58H”? Y (4)Burst data transfer N (5)Read more sectors? Y Preliminary version THNCFxxxMAA Series I/O Access, INDEX=1 2001-09-05 37/52 ...
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... I/O interface is shown as follows. ( A10 -CE1 -CE2 -IOWR -IORD 01H20H D0H→ → → → 58H (Data transfer D15 -IREQ (3) (4) ( Preliminary version THNCFxxxMAA Series ( D0H→ → → → 50H 2001-09-05 38/52 ...
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... Read 256 times the data register all data write Y N Read the status register N “51H” Y error handle Wait the command input Start (1)Set the logical sector number (2) (3) “58H”? Y (512 bytes) (4)Burst data transfer N Y (5) “50H”? Y Preliminary version THNCFxxxMAA Series I/O Access, INDEX=1 2001-09-05 39/52 ...
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... Max Max Max Unit Unit Unit Unit Test conditions Test conditions Test conditions Test conditions － Vin=0V － Vout=0V Preliminary version THNCFxxxMAA Series (5) 7H Unit Unit Unit Unit Note Note Note Note °C °C Max Max Max Max ...
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... Set up times (Deep power down to idle) Data transfer rate to/from host Sustained read transfer rate Sustained write transfer rate Controller overhead (Command to DRQ) Data transfer cycle end to ready(Sector write) Preliminary version THNCFxxxMAA Series Performance Performance Performance Performance 500 ms (max) 100 μs (max) ...
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... T clkh Parameter Parameter Parameter Parameter Min Min Min Min 20 20 Preliminary version THNCFxxxMAA Series Unit Unit Unit Unit Test conditions Test conditions Test conditions Test conditions V － =3. =-4mA =4mA OL μ ...
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... tsu ( Preliminary version THNCFxxxMAA Series = 3.3V±5%) = 3.3V = 3.3V = 3.3V 5%) 5%) 5 Unit Unit Unit Unit tdls ( CE ) tdls ( OE ) ...
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... Attribute Memory Write Timing Attribute Memory Write Timing Attribute Memory Write Timing Attribute Memory Write Timing -Reg An tsu(A) tsu(A) tsu(A) tsu(A) -WE -CE -OE Din Preliminary version THNCFxxxMAA Series Min Min Min Min Typ Typ Typ Typ Max Max Max Max Unit Unit ...
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... Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit 45 ns － ns － ns － ns － ns － ns － ns － ...
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... Din Valid Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit － ns － ns － ns － ns － ns － ns － ns － ns － ...
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... Min Min Min Min Typ Typ Typ Typ ta(OE) － － tdis(OE) － － tsu(A) 30 － th(A) 20 － tsu(CE) 0 － th(CE) 0 － tsu(A) tsu(CE) ta(OE) Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit － ns － ns － ns － ns th(A) th(CE) tdis(OE) 2001-09-05 47/52 ...
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... Typ Typ Typ Typ tsu(D-WEH) 40 － th(D) 30 － tw(WE) 80 － tsu(A) 30 － tsu(CE) 0 － trec(WE) 20 － th(CE) 0 － tsu(A) tsu(CE) tw(WE) Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit － ns － ns － ns － ns － ns － ns － ns th(A) th(CE) trec(WE) th(D) Din Valid 2001-09-05 48/52 ...
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... Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit 45 ns － ns － ns － ns － ns － ns － ...
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... Preliminary version THNCFxxxMAA Series Max Max Max Max Unit Unit Unit Unit － ns － ns － ns － ns － ns － ns － ...
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... Low Preliminary version THNCFxxxMAA Series Unit Unit Test Test Unit Unit Test Test conditions conditions conditions conditions ms µ µ tpr 90% trec(Vcc) 10% ts(Hi-ZRESET) ...
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... V to the card. CC Note: level during power on reset in memory card mode and I/O card mode. –OE must be -OE must be kept at the V CC kept constantly at the GND level in True IDE mode. Preliminary version THNCFxxxMAA Series . CC Min Min Typ Typ Max Max ...