THNCFxxxMAA Toshiba, THNCFxxxMAA Datasheet - Page 18

• Manufacturer Part Number: THNCFxxxMAA
• Description: Small Form Factor Card
• Manufacturer: Toshiba

2. 2. 2. 2. Configuration and Status register (
This register is used for observing the state of the card.
bit7
bit7
bit7
bit7
CHGED
Note: initial value: 00H
Name
Name
Name
Name
CHGED
(CARD->)
SIGCHG
(HOST->)
IOIS8
(HOST->)
PWD
(HOST->)
INTR
(CARD->)
Configuration and Status register (
Configuration and Status register (
Configuration and Status register (Address 202H)
bit6
bit6
SIGCHG
R/W
R/W
R
R/W
R/W
R/W
R
bit6
bit6
R/W
R/W
Function
Function
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to “1”.
When CHGED bit is set to “1”, -STSCHG pin is held “L” at the condition of
SIGCHG bit set to “1” and the card configured for the I/O interface.
This bit is set or reset by the host for enabling and disabling the status-change
signal (-STSCHG pin). When the card is configured I/O card interface and this bit
is set “1”, -STSCHG pin is controlled by CHGED bit. If this bit is set to “0”,
-STSCHG pin is kept “H”.
The host sets this field to “1” when it can provide I/O cycles only with on 8 bit
data bus (D7 to D0).
When this bit is set to “1”, the card enters sleep state (Power Down mode). When
this bit is reset to “0”, the card transfers to idle state (active mode). RRDY/BSY
bit on Pin Replacement Register becomes BUSY when this bit is changed.
RRDY/BSY will not become Ready until the power state requested has been
entered. This card automatically powers down when it is idle and powers back up
when it receives a command.
This bit indicates the internal state of the interrupt request. This bit state is
available whether I/O card interface has been configured or not. This signal
remains true until the condition, which caused the interrupt request, has been
serviced. If the –IEN bit in the Device Control Register disables interrupts, this bit
is a zero.
Function
Function
bit5
bit5
IOIS8
bit5
bit5
Address 202H)
Address 202H)
Address 202H)
bit4
bit4
bit4
bit4
0
bit3
bit3
bit3
bit3
0
bit2
bit2
PWD
bit2
bit2
THNCFxxxMAA Series
bit1
bit1
INTR
bit1
bit1
Preliminary version
2001-09-05 18/52
bit0
bit0
bit0
bit0
0