HYS64D16020GDL-7-A Infineon, HYS64D16020GDL-7-A Datasheet - Page 20
HYS64D16020GDL-7-A
Manufacturer Part Number
HYS64D16020GDL-7-A
Description
Unbuffered DDR SDRAM SO Modules
Manufacturer
Infineon
Datasheet
1.HYS64D16020GDL-7-A.pdf
(22 pages)
Table 11
Byte#
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
46 to 61
62
63
64
65 to 71
72
73 to 90
91 to 92
93 to 94
95 to 98
99 to 127
128 to 255
Data Sheet
SPD Codes for PC2100 & PC1600 (cont’d)
Description
Minimum Row Act. to Row Act.
Delay
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Module Rank Density (per Rank) 64 MByte
Addr. and Command Setup Time 0.9 ns/1.1 ns
Addr. and Command Hold Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time
Min. Auto Refresh Cmd Cycle
Time
Maximum Clock Cycle Time
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufactures JEDEC ID Codes
Manufactures
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
open for Customer use
t
t
FRC
RRD
t
t
RC
RAS
t
t
CK
RCD
15 ns
20 ns
45 ns/50 ns
0.9 ns/1.1 ns
0.5 ns/0.6 ns
0.5 ns/0.6 ns
–
65 ns/70 ns
75 ns/80 ns
12 ns
0.5 ns/0.6 ns
0.75 ns/1.0 ns
–
Revision 0.0
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20
Unbuffered DDR SDRAM SO Modules
HYS64D16020GD(L)-[7/8]-A
128MB
x64
2ranks
–7
HEX.
3C
50
2D
10
90
90
50
50
41
4B
30
32
75
00
00
88
C1
Infineon
–
–
–
–
–
–
–
11042003-YIV7-VK6M
Rev. 1.02, 2004-01
SPD Contents
128MB
x64
2ranks
–8
HEX.
3C
50
32
10
B0
B0
60
60
46
50
30
3C
A0
00
00
7D
C1
Infineon
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–
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