HYS64D64320HU-5-C Infineon, HYS64D64320HU-5-C Datasheet - Page 8
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HYS64D64320HU-5-C
Manufacturer Part Number
HYS64D64320HU-5-C
Description
184-Pin Unbuffered Double Data Rate SDRAM
Manufacturer
Infineon
Datasheet
1.HYS64D64320HU-5-C.pdf
(41 pages)
2
The pin configuration of the Unbuffered DDR SDRAM
DIMM is listed by function in
abbreviations used in columns Pin and Buffer Type are
explained in
numbering is depicted in
Table 3
Pin# Name
Clock Signals
137
16
76
138
17
75
21
111
Control Signals
157
158
154
65
63
Address Signals
59
52
48
43
41
130
37
32
125
29
Data Sheet
CK0
NC
CK1
CK2
CK0
NC
CK1
CK2
CKE0
CKE1
NC
S0
S1
NC
RAS
CAS
WE
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
Table 4
Pin Configuration
Pin Configuration of UDIMM
Pin
Type
I
NC
I
I
I
NC
I
I
I
I
NC
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
and
Buffer
Type
SSTL
—
SSTL
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Figure
Table 5
Table 3
Function
Clock Signals 2:0
Note: For
Complement Clock
Signals 2:0
Note: For
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address
Strobe
Write Enable
Bank Address Bus
2:0
Address Bus 11:0
1.
respectively. The pin
loading see block
diagram, CK0 is
NC on 1R
loading see block
diagram, CK0 is
NC on 1R
(184 pins). The
clock
clock
!
!
HYS[64/72]D[16/32/64][300/301/320][G/H]U[5/6]C
16
16
net
net
8
Table 3
Pin# Name
122
27
141
118
115
167
Data Signals
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
A8
A9
A10
AP
A11
A12
NC
A13
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
Unbuffered DDR SDRAM Modules
Pin Configuration of UDIMM (cont’d)
Pin
Type
I
I
I
I
I
I
NC
I
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Address Bus 11:0
Address Signal 12
Note: Module based on
Note: 128 Mbit
Address Signal 13
Note: 1 Gbit
Note: Module based on
Data Bus 63:0
Pin Configuration
256 Mbit or larger
dies
module
module
512 Mbit
smaller dies
Rev. 1.0, 2004-03
based
based
or