EVAL-ADE7816EBZ AD [Analog Devices], EVAL-ADE7816EBZ Datasheet - Page 30

• Manufacturer Part Number: EVAL-ADE7816EBZ
• Description: Six Current Channels, One Voltage Channel
• Manufacturer: AD [Analog Devices]

ADE7816
CHECKSUM
The
that ensures that certain important configuration registers maintain
their desired value during normal operation.
The registers that are included in this feature are MASK0,
MASK1, COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, HSDC_CFG, plus four additional 16-bit reserved
registers and six 8-bit reserved internal registers. All reserved
registers always have default values. The
cyclic redundancy check (CRC) based on the IEEE802.3 standard.
The registers are introduced, one by one, into a linear feedback
shift register (LFSR) based generator, starting with the least
significant bit (as shown in Figure 36). The 32-bit result is written
in the checksum register. After power-up or a hardware/software
reset, the CRC is computed on the default values of the registers.
The default value of the checksum register is 0x33666787.
Figure 37 shows how the LFSR works. The MASK0, MASK1,
COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, and HSDC_CFG registers, along with the four
16-bit reserved registers and six 8-bit reserved internal registers,
form the Bits[a
significant bit of the first internal register to enter the LFSR;
Bit a
register to enter the LFSR. The formulas that govern the LFSR
are as follows:
b
form the CRC. Bit b
most significant bit.
i
(0) = 1, where i = 0, 1, 2, …, 31, the initial state of the bits that
ADE7816
255
is the most significant bit of the MASK0 register, the last
31
255 248
MASK0 MASK1 COMPMODE
has a 32-bit checksum register (Address 0xE51F)
255
, a
0
254
0
31
, …, a
is the least significant bit, and Bit b
240
0 15
0
] used by the LFSR. Bit a
232
LFSR
0 15
g
0
GAIN
224
ADE7816
b
0
0
Figure 37. LFSR Generator Used in Checksum Register Calculation
15
RESERVED
g
1
216
computes the
0
0
Figure 36. Checksum Register Calculation
is the least
b
1
31
7
INTERNAL
REGISTER
is the
g
2
Rev. 0 | Page 30 of 48
40
b
0 7
2
REGISTER
INTERNAL
g
3
g
polynomial defined by the IEEE802.3 standard as follows:
All of the other g
Equation 20, Equation 21, and Equation 22 must be repeated for
j = 1, 2, …, 256. The value written into the checksum register con-
tains Bit b
internal register pass through the LFSR, the value of the CRC
(which is obtained at Step j = 48) is 0x33660787.
Two different approaches can be followed in using the checksum
register. One is to compute the CRC, based on Equation 18 to
Equation 22, and then compare the value against the checksum
register. Another is to periodically read the checksum register.
If two consecutive readings differ, it can be assumed that one of
the registers has changed value and that, therefore, the
configuration has changed. The recommended response is to
initiate a hardware/software reset that sets the values of all
registers (including the reserved ones) to the default, and then
reinitialize the configuration registers.
i
32
, where i = 0, 1, 2, …, 31 is the coefficient of the generating
a
0 7
255
G(x) = x
x
g
g
FB(j) = a
b
b
INTERNAL
REGISTER
,
0
8
8
0
i
a
(j) = FB(j) AND g
(j) = FB(j) AND g
= g
= g
254
+ x
,....,
g
i
1
10
7
(256)
31
= g
+ x
a
24
= g
0
2
32
,
j − 1
a
2
5
+ x
11
INTERNAL
REGISTER
7
1
b
= g
,
+ x
,
31
XOR b
i = 0, 1, …, 31. After the bits from the reserved
i
a
= g
coefficients are equal to 0.
0
26
4
4
= g
12
+ x
+ x
16
= g
0
5
23
2
31
i
= g
0
XOR b
+ x + 1
16
(j − 1)
+ x
INTERNAL
REGISTER
FB
7
= g
7
22
= 1
GENERATOR
22
+ x
i − 1
= g
LFSR
0
8
16
(j − 1), i = 1, 2, 3, ..., 31
26
+ x
INTERNAL
REGISTER
7
7
= g
12
31
+ x
= 1
0
0
11
+ x
Data Sheet
10
+
ADE7816
(18)
(19)
(20)
(21)
(22)