EVAL-ADE7816EBZ AD [Analog Devices], EVAL-ADE7816EBZ Datasheet - Page 32

• Manufacturer Part Number: EVAL-ADE7816EBZ
• Description: Six Current Channels, One Voltage Channel
• Manufacturer: AD [Analog Devices]

ADE7816
I
The read operation, using the I
accomplished in two stages. The first stage sets the pointer to
the address of the register; the second stage reads the contents
of the register (see Figure 40).
The first stage is initiated when the master generates a start con-
dition. It consists of one byte, representing the address of the
ADE7816, followed by the 16-bit address of the target register. The
ADE7816
similar to the address byte of a write operation and is equal to 0x70
(see the I
byte of the register address is sent and acknowledged by the
ADE7816, the second stage begins with the master generating
a new start condition, followed by an address byte. The most
significant seven bits of this address byte constitute the address of
the ADE7816, which is 0111000b. Bit 0 of the address byte is a
read/ write bit. Because this is a read operation, it must be set to 1;
therefore, the first byte of the read operation is 0x71. After this byte
is received, the
ADE7816
are received, the master generates an acknowledge. All the bytes
are sent with the most significant bit first. Registers can be 8, 16,
or 32 bits. After the last bit of the register is received, the master
does not acknowledge the transfer but, instead, generates a stop
condition.
2
C Read Operation
S
S
2
C Write Operation section for details). After the last
0
acknowledges every byte received. The address byte is
sends the value of the register, and, after every eight bits
0
SLAVE ADDRESS
S
1 1 1 0 0 0 0
SLAVE ADDRESS
1 1 1 0 0 0 0
0
ADE7816
1 1 1 0 0 0 1
SLAVE ADDRESS
generates an acknowledge. Then the
A
C
K
15
REGISTER ADDRESS
A
C
K
ACKNOWLEDGE
GENERATED BY
MS 8 BITS OF
15
REGISTER ADDRESS
2
ADE7816
C interface of the ADE7816, is
MSB 8 BITS OF
A
C
K
31
8
BYTE 3 (MSB)
A
C
K
OF REGISTER
ACKNOWLEDGE
GENERATED BY
7
REGISTER ADDRESS
ADE7816
LS 8 BITS OF
8
Figure 39. I
A
C
K
Figure 40. I
7
REGISTER ADDRESS
LSB 8 BITS OF
16
0
A
C
K
2
A
C
K
2
C Write Operation of a 32-Bit Register
C Read Operation of a 32-Bit Register
15
31
Rev. 0 | Page 32 of 48
OF REGISTER
BYTE 3 (MS)
BYTE 2 OF
REGISTER
0
ACKNOWLEDGE
GENERATED BY
A
C
K
ADE7816
16
ACKNOWLEDGE
GENERATED BY
SPI-Compatible Interface
The
consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA,
MISO/HSD, and SS /HSA. The functions used in the SPI-compatible
interface are SCLK, MOSI, MISO, and SS . The serial clock for
a data transfer is applied at the SCLK logic input. This logic input
has a Schmitt trigger input structure that allows the use of slow
rising (and falling) clock edges. All data transfer operations
synchronize to the serial clock. Data shifts into the
at the MOSI logic input on the falling edge of SCLK, and the
ADE7816
of the
and can be sampled by the master device on the raising edge of
SCLK. The most significant bit of the word is shifted in and out
first. The maximum serial clock frequency that is supported by
this interface is 2.5 MHz. MISO stays in high impedance when no
data is transmitted from the
the connection between the
containing a SPI interface.
A
C
K
15
BYTE 2 OF REGISTER
MASTER
8
ADE7816
A
C
K
ADE7816
7
Figure 38. Connecting the
samples it on the rising edge of SCLK. Data shifts out
BYTE 1 OF
REGISTER
SPI is always a slave of the communication and
ADE7816
8
at the MISO logic output on a falling edge of SCLK
A
C
K
BYTE 1 OF REGISTER
MOSI/SDA
MISO/HSD
SCLK/SCL
7
SS/HSA
0
ADE7816
ADE7816
A
C
K
ADE7816
7
0
A
C
K
MOSI
MISO
SCK
SS
OF REGISTER
BYTE 0 (LSB)
7
.
SPI DEVICE
SPI and a master device
Figure 38
BYTE 0 (LS) OF
SPI with a SPI Device
REGISTER
Data Sheet
shows details of
0
0
A
C
K
N
O
A
C
K
ADE7816
S
S