EVAL-ADE7816EBZ AD [Analog Devices], EVAL-ADE7816EBZ Datasheet - Page 33

• Manufacturer Part Number: EVAL-ADE7816EBZ
• Description: Six Current Channels, One Voltage Channel
• Manufacturer: AD [Analog Devices]

Data Sheet
The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. Drive the SS input
low for the entire data transfer operation. Bringing SS high
during a data transfer operation aborts the transfer and places
the serial bus in a high impedance state. A new transfer can
then be initiated by returning the SS logic input to low. However,
because aborting a data transfer before completion leaves the
accessed register in a state that cannot be guaranteed, the value of a
register should be verified by reading it back each time it is written.
The protocol is similar to the protocol used with the I
SPI Read Operation
The read operation, using the SPI interface, initiates when the
master sets the SS /HSA pin low and begins sending one byte,
representing the address of the
master sets data on the MOSI line starting with the first high-to-
low transition of SCLK. The
low-to-high transitions of SCLK. The most significant seven bits
of the address byte can have any value, but, as good programming
practice, they should be different from 0111000b, the seven bits
used in the I
be set to 1 for a read operation. Next, the master sends the 16-bit
address of the register to be read. After the
last address bit of the register on a low-to-high transition of SCLK,
2
C protocol. Bit 0 (read/
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SCLK
MOSI
MISO
SCLK
MOSI
write ) of the address byte must
SS
SS
SPI samples data on the
, on the MOSI line. The
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0
0
0
0
Figure 41. SPI Read Operation of a 32-Bit Register
Figure 42. SPI Write Operation of a 32-Bit Register
0
0
2
0
0
C interface.
receives the
0 0 0
0 0 0 0
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1
15 14
REGISTER ADDRESS
15 14
REGISTER
ADDRESS
it begins to transmit its contents on the MISO line when the next
SCLK high-to-low transition occurs; thus, the master can sample
the data on a low-to-high SCLK transition. After the master
receives the last bit, it sets the
communication ends. The data lines, MOSI and MISO, go into
a high impedance state (see
SPI Write Operation
The write operation, using the SPI interface, initiates when the
master sets the SS /HSA pin low and begins sending one byte,
representing the address of the
master sets data on the MOSI line, starting with the first high-to-
low transition of SCLK. The SPI samples data on the low-to-high
transitions of SCLK. The most significant seven bits of the address
byte can have any value, but, as a good programming practice,
they should be different from 0111000b, the seven bits that are used
in the I
for a write operation. Next, the master sends the 16-bit address
of the register that is written and the 32-, 16-, or 8-bit value of that
register without losing any SCLK cycle. After the last bit is trans-
mitted, the master sets the SS and SCLK lines high at the end of
the SCLK cycle and the communication ends. The data lines, MOSI
and MISO, go into a high impedance state (see
1 0
1 0 31 30
31 30
2
C protocol. Bit 0 (read/
REGISTER VALUE
REGISTER VALUE
1 0
1 0
Figure 41
write ) of the address byte must be 0
SS and SCLK lines high, and the
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).
, on the MOSI line. The
Figure 42
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).