DM74AS286N Fairchild Semiconductor, DM74AS286N Datasheet

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... Package Number DM74AS286M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74AS286N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

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Switching Characteristics over recommended supply and temperature range Symbol Parameter t Propagation Delay Time PLH from LOW-to-HIGH Level Output t Propagation Delay Time PHL from HIGH-to-LOW Level Output t Propagation Delay Time PLH from LOW-to-HIGH Level Output t Propagation Delay ...

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Typical Applications (Continued) Direction Control Direction (XMIT) (Parity I/O) H (Receive) L (Transmit) L LOW Logic Level H HIGH Logic Level N/A Not Applicable FIGURE 2. Bus I/O Parity Implementation www.fairchildsemi.com I/O Parity Check Result (Parity Error) Level Input H ...

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Typical Applications (Continued) Note: Parity format in this configuration is “odd parity” FIGURE 3. 90-Bit Parity Generator/Checker Implementation Using Device Expansion Techniques 5 www.fairchildsemi.com ...

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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 6 ...

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...