DM74AS280MX Fairchild Semiconductor, DM74AS280MX Datasheet
DM74AS280MX
Specifications of DM74AS280MX
Related parts for DM74AS280MX
DM74AS280MX Summary of contents
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features Generates either odd or even parity for nine data lines ...
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Logic Diagram www.fairchildsemi.com 2 ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...
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Typical Applications Three DM74AS280s can be used to implement a 25-line parity generator/checker alternative, the outputs of two or three parity genera- tors/checkers can be decoded with a 2-input (AS86 FIGURE 2. 81-Line Parity/Generator Checker www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...