ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 27

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
2.6
DVI_PLL_6
DVI_PLL_7
DVI_PLL_8
DVI_PLL_9
DVI_PLL_10
HDCP Block
The HDCP block implements the datapath decryption block of the HDCP content protection scheme
of DVI. Please refer to the HDCP Specification 1.0 for details. The state machines of the HDCP
specification are split between the external microcontroller and this block. Only the high speed and
data intensive cryptographic functions are implemented in this block to maintain maximum system
level flexibility.
Register Name
0x0486
0x0487
0x0488
0x0489
0x048A
Table 9: DVI Registers (Sheet 5 of 5)
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Mode
[7:6]
[5:4]
[3:2]
[1:0]
[7:6]
[5:4]
[3:2]
[1:0]
[7:6]
[5:4]
[3:2]
[1:0]
[7:6]
[5]
[4]
[3:2]
[1:0]
[3:2]
[1:0]
[7]
[6:4]
[3:0]
[3:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
Strobe [16:19] Delay Adjustment
0x0: Normal
0x1: Slow
0x2: Fast
0x3: Reserved
Strobe [20:23] Delay Adjustment
0x0: Normal
0x1: Slow
0x2: Fast
0x3: Reserved
Strobe [24:27] Delay Adjustment
0x0: Normal
0x1: Slow
0x2: Fast
0x3: Reserved
Reserved
Test Enable (normal operation = 0)
Strobe Delay Adjustment Step
0: 45pS (default)
1: 72pS
Strobe 29 Adjust
0: Normal
1: Slower
2: Faster
3: Reserved
Strobe 28 Adjust
Strobe [28:29] Delay Adjustment
0x0: Normal
0x1: Slow
0x2: Fast
0x3: Reserved
Reserved
Test Output DVIPLL[79:77]
PLL Range Status
PLL Range Status
Description
HDCP Block
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