ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 32

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Sync Measurement Block
32/88
2.9
SMEAS_ACT_CTRL
SMEAS_ACT_H_SMPTM_L
SMEAS_ACT_H_SMPTM_H
SMEAS_ACT_V_SMPTM_L
SMEAS_ACT_V_SMPTM_H
SMEAS_ACT_H_MINEDGE
SMEAS_ACT_V_MINEDGE
SMEAS_H_TMOT_L
SMEAS_H_TMOT_H
SMEAS_V_TMOT_L
SMEAS_V_TMOT_H
Sync Measurement Block
The Input Sync Measurement Block (SMEAS) continuously detects activity from all video sources.
The module can measure the characteristics of the sync signals on any input port. The sync
measurement module reports the results of the measurements to the system microcontroller.
This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another
block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming
sync signals.
Input Sync Functions:
Register Name
Activity detection
Sync management
Measurement
Table 13: Sync Measurement Registers (Sheet 1 of 8)
0x0100
0x0102
0x0104
0x0105
0x0107
0x0108
0x0109
0x010A
0x0101
0x0103
0x0106
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7:4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x4000
0x1600
Reserved
Enable activity detection in Free-running
mode.
Freeze results in Free-running mode. No
meaning in One-shot mode.
0: Do not freeze the results. New result will
be available on the next and subsequent
toggle of the polling bit.
1: Freeze the current results. The polling bit
will still toggle and the block continues to free
run; however, results will not be updated.
activity detection start.
In one-shot mode it triggers the start of a
measurement and is reset to zero when the
measurement is complete.
activity detection mode control
0: free run
1: one shot
Sample time value for clock or hsync activity.
In units of XCLK_period*256
Sample time value for vsync activity in units
of XCLK_period*256.
Note: this number MUST be larger than
hsync sample time.
Minimum edge count value for clk or hsync
activity.
Minimum edge count value for vsync activity.
timeout counter value for clk or horizontal
measurement in XCLKs
timeout counter value for vertical
measurement in units of XCLK/256
Description
ADE3XXX