ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 75

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
2.23
OMUX_CTRL_0
OMUX_CTRL_1
APC_APC0
APC_APC1
Output Mux Block
Register Name
Register Name
Table 29: Output Mux Registers (Sheet 1 of 3)
0x0C30
0x0C31
0x0C20
0x0C21
Addr
Addr
Table 28: APC Registers
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
Mode
[7]
[6:4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6:5]
[4:1]
[0]
[7:2]
[1]
[0]
Bits
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
Default
Reserved
Frame Modulation Period - 1
0x0 - 0x3: 8b Out
0x4: 4-bit Output
0x5: 5-bit Output
0x6: 6-bit Output
0x7: 7-bit Output
0x8: 8-bit Output
0: normal
1: disable APC -- truncate LSBs
Reserved
Offset the Phase LUT
Offset the Dither LUT
in 2 ppc,
0: data invert for A+B comb.
1: data invert A/B separate
0x0 - 0x4: right shift per 8b R/G/B
0x5 - 0x7: Reserved
0: normal
1: flip MSBs to LSBs
0: normal
1: swap R and B data
0: in 1 ppc, A channel active
0: in 2 ppc, Left on A, Right on B
1: in 1 ppc, B channel active
1: 2ppc, Left on B, Right on A
0: single wide, one pix/clk (ppc)
1: double wide, two pix/clk
Vsync Output Polarity
Hsync Output Polarity
Data Enable Output Polarity
Clock Output Invert
Data Invert Output Polarity
Data Invert Enable
0: TCON outputs set to zero
1: TCON outputs active
0: all data outputs set to zero
1: output enabled
Description
Description
Output Mux Block
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