MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 17

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT90222 Pin Description (continued)
D13,D17,N23,U
N25,H26,F26,A
23,D20,C16,A1
P2,T3,Y2,AB3,
E2,H1,J1,M3,
D6,D10,D14,
D22,E23,F4,
K23,N4,P23,
AC16,AE16,
AD12,AD15,
AC19,AD25,
AC06,AC13,
AC17,AC22,
AC14,K4,P4
AF16,AC15,
AE15,AF15,
AA23,AB04,
AD14,AE14
AA25,V26,
AE6,AF8,
23,AC10,
3,A8,C5
Pin #
AF14
AC1
C19
AD1
D19
D7
C6
C7
U4
A4
A5
B6
B5
B4
Data[7:0]
LatchClk
RXRing
RXRing
Name
Reset
TRST
VDD5
Test1
Test2
Test3
Test4
Sync
TMS
TDO
V3.3
V2.5
TCK
TDI
Clk
I/O
O
O
O
S
S
S
I
I
I
I
I
I
I
I
I
I
I
TDM Ring RX Sync. Synchronization input signal used to retrieve data and control
from the bytes on RXRingData. Should be connected to the TXRingSync output of the
previous MT90222 device in the Ring. There is an internal weak pull-down on this
input. NOT 5 V TOLERANT.
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM
Ring port. Should be connected to the TXRingData inputs of the previous MT90222
device in the Ring. There are internal weak pull-downs on these inputs. NOT 5 V
TOLERANT.
System Clock (50 MHz nominal). In the MT90222, this clock is used for all internal
operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally to
produce the latch signal for the internal counters. Refer to the Counter Transfer
Command register for more details. This pin has an internal pull-down.
System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Data Output. Note: TDO is tristated by TRST pin.
JTAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak
pull-down.
Test1. Must be tied Low
Test2. Must be left not connected (NC).
Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT.
Test4. Must be left not connected (NC)
5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals,
otherwise, connect to a 3.3 Volt supply.
3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
Zarlink Semiconductor Inc.
MT90222/3/4
System Signals
Power Signals
17
Description
Data Sheet