MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 63

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Overflow conditions in the RX UTOPIA FIFO associated with any of the 24 PHY RX Addresses cause a status bit to
be set in either the IRQ Link TC Overflow Status (0x0410-0x041F) or IRQ IMA Overflow Status Registers
(0x0420-0x0427) register. These status bits are cleared by overwriting them with 0. Additionally, for each status bit
there is an Interrupt Enable bit in the associated IRQ Link TC Overflow Enable (0x0434) or RX UTOPIA IMA
Group FIFO Overflow IRQ Enable (0x040C) register. When enabled, the status bit is reported in an Interrupt
register. See section 6.2 Interrupt Block for more details.
The size of the RX UTOPIA FIFO is fixed at four cells for the TC PHY and IMA Group PHY Addresses.
Note that in the receive direction, the parity bit that is generated is not valid if the receive Utopia clock is faster than
50 MHz.
5.3
A single ATM layer device with a UTOPIA L2 MPHY port can be connected to the ATM input port of one
MT90222/3/4. Another ATM-Layer device using the UTOPIA L2 MPHY input interface is used to receive ATM cells
from the MT90222/3/4.
The address pins should be set to the value programmed by the management interface.
5.4
When more than one MT90222/3/4 is connected to a single ATM Layer device the single TxClav and RxClav scheme
is used. Direct Status Indication and Multiplexed Status Polling schemes are not supported. The necessary polling
is performed by the ATM-Layer device.
The UTOPIA Interface transmit and receive addresses, provided by the ATM-Layer device, are used to de-multiplex
the ATM-cell stream to as many as eight MT90222/3/4s (as limited by the UTOPIA L2 specification’s maximum of
eight device loads and 31 addresses). The maximum total available bandwidth for the serial lines served by each
MT90222/3/4 device is 40 Mbits/s (totalling 5 MBytes/s per MT90222/3/4 device).
5.5
In TC Mode, each Utopia port inside an MT90222/3/4 corresponds to a physical serial TDM (T1, E1, J1, DSL) line.
Up to sixteen PHY ports can be supported by one MT90224. Up to eight MT90222/3/4s can be connected to a
UTOPIA bus. The ports in the same device represent only one electrical load on the UTOPIA bus. The MT90222/3/4
supports the up to 31 PHY addresses as per UTOPIA specification.
Please also refer to Technical Note ZLAN-88: UTOPIA Interface between MT90224/3/2 and Specific ATM
Controllers, as there might be some limitations on maximum number of PHY addresses supported depending on the
type of ATM controller that is interfaced with MT90224/3/2.
The MPHY address at the input port of MT90222/3/4 (TxAddr[4:0]) is used to store the cell in one specific TX UTOPIA
FIFO.
The MPHY address at the output port (RxAddr[4:0]) is used to retrieve the cells from the proper RX UTOPIA FIFO.
UTOPIA Operation with a Single PHY
UTOPIA Operation with Multiple PHY
UTOPIA Operation in TC Mode
Zarlink Semiconductor Inc.
MT90222/3/4
63
Data Sheet