MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 39

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.4.7
Once per IMA frame, an ICP cell is transmitted on each link of the IMA Group. The content of the ICP cell is
controlled both by MT90222/3/4 and software. The software content of the ICP cell bytes is stored in buffer RAM. A
copy of the ICP cell for each group is kept in the internal Transmitter Cell RAM.
The ICP cell to be transmitted on each link is assembled on an as required basis under the control of the internal
RoundRobin scheduler and ICP Cell Modifier.
Hardware controls the following bytes of the ICP cell:
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Software controls all remaining bytes of the ICP cells. It also maintains and updates all bytes that are not directly
controlled by the MT90222/3/4. A dedicated address is reserved for each ICP cell byte for each of the eight IMA
Groups. This permits direct access to any of the bytes stored in each of the eight ICP Cell registers. Refer to
Table 2, ICP Cell Description, for details on the ICP cell byte contents.
To avoid updating or corruption problems, the internal copy of the ICP Cell cannot be directly accessed. ICP cells
are prepared in a buffer area (RAM inside the MT90222/3/4) and transfer commands are issued to copy the content
of the ICP cell into the internal Cell RAM area and to start using this new ICP cell. The MT90222/3/4 uses a flag
(status bit) to indicate that this transfer is underway. Changes should not be made to the content of the ICP cell in
the buffer area until the transfer to the internal memory is complete. The status bit is cleared during the transfer and
returns to ’1’ on completion of the transfer. IMA Groups are controlled independently. When access to the ICP cell
of one group is prohibited, the other ICP cell buffer areas can still be updated. The TX ICP Cell Handler (0x0086)
and TX ICP Cell Interrupt Enable (0x0088) registers are used to initiate a transfer and enable an optional interrupt
to indicate when the process is complete.
The SCCI field is incremented by one for each transfer command performed which includes a change in at least
one byte of the ICP cell.
2.4.8
An optional interrupt is provided at the end of an IMA frame to simplify software implemented changes in the Group
Control and Status field. This interrupt can be enabled on an as required and per group basis to implement a frame
counter. The TX IMA Frame Indication (0x0087) and TX IMA Frame Interrupt Enable (0x0089) registers are
used for the end of frame indication and frame interrupt.
Byte 5 - the HEC is always calculated and inserted by the MT90222/3/4
Byte 6 - the TX OAM Label is defined by the software and the value contained in this location is transmitted
in all ICP cells, Stuff Cells and Filler cells sent on all the links that are part of the corresponding TX IMA
group
Byte 7 - the TX Link ID (0x0336 - 0x033D) registers are used to set the Link Logical ID and the cell type is
determined by the internal controller on a per link basis
Byte 8 - the frame sequence number is controlled by an internal counter
Byte 9 - the TX ICP Cell Offset (0x0310-0x0317) registers are used to set this value and is inserted on a per
link basis
Byte 10 - the link Stuff indication is inserted automatically and the advance indication option is programmed
by the TX IMA Control (0x0321-0x0324) registers on a per link basis
Byte 11 - the SCCI is controlled by internal circuitry. The SCCI is incremented by one for each transfer of the
TX ICP cell from the buffer area to the TX Cell RAM.
Byte 13 - the value of M is programmed through the TX Group Control Mode (0x0300-0x0307) register
Byte 14 - the TX Group Control Mode (0x0300-0x0307) register is used to set the Transmit Timing
Information and define the reference link
Bytes 52 and 53 - the calculated CRC-10 Error Control bits are inserted automatically
ICP Cell Generator
IMA Frame Programmable Interrupt
Zarlink Semiconductor Inc.
MT90222/3/4
39
Data Sheet