MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 97

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
15:3
10:6
4:0
11
2
1
0
5
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Unused. Read all 0’s.
Ring Enable:
0: RING is NOT used and the output tri-state buffers are disabled (High Z mode).
1: RING is used and the output tri-state buffers are enabled (active).
Ring Initialization: Valid only for Ring Master
0: RUN mode.
1: INITIALIZATION mode. The MASTER device generates empty HEADER bytes to
initialize the RING.
Ring Master
0: This device is not the MASTER of the RING.
1: This device is the MASTER of the RING (Only 1 device can be MASTER on a RING)
Unused. Read 0.
ATM side:
0: Normal mode. The external RING is not connected to the ICP Cell Modifier.
1: RING mode. The external RING is connected to the ICP Cell Modifier.
Tx Link Ring Address assigned to the ATM mode switch.
TDM side:
0: Normal mode. The external RING is not connected to the TDM Tx Interface.
1: RING mode. The external RING is connected to the TDM Tx Interface.
Tx Link Ring Address assigned to the TDM mode switch.
0x0180 (1 reg)
1 register for TDM Ring Tx.
0000
0x0181 - 0x0190 (16 reg)
1 register per Tx Link.
0000
Table 53 - Ring Tx Control Register
Table 54 - Ring Tx Link Registers
Zarlink Semiconductor Inc.
MT90222/3/4
97
Description
Description
Data Sheet