MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 70

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

another interrupt service request, if necessary. At the end of this process, the enable bit in the IRQ Link Enable
(0x0445-0x0454) register would be set to ’1’ to detect any future interrupt requests.
6.2.2.1
Bits 8 and 7 of the IRQ Link 0 Status (0x0435) register have a special operation.
Bit 8 reports an overflow condition in any of the counters or UTOPIA RX FIFOs associated with one of the eight IMA
Groups. Refer to IRQ IMA Group Overflow Status (0x0457) and IRQ IMA Group Overflow Enable (0x040B)
registers for more details. Bit 8 is a status bit and is cleared by disabling the IRQ for this specific counter or disabling
(masking) the FIFO overflow condition by writing to the RX UTOPIA IMA Group FIFO Overflow IRQ Enable
(0x040C) register.
Bit 7 is used to report the following two event types:
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The second type of event assists in implementing the software counter required to verify that Group Status and
Control field information is sent for at least 2 consecutive IMA frames.
The sixteen interrupt sources are enabled independently by writing to the TX ICP Cell Interrupt Enable (0x0088)
register and the TX IMA Frame Interrupt Enable (0x0089) register. Note that both interrupts from the IMA Frame
and the ICP Cell internal transfer have to be enabled for an interrupt to be generated.
There is also an associated Control/Status register (TX ICP Cell Handler (0x0086) register) that reports the interrupt
source and the state of the transfer of an ICP Cell or the occurrence of the end of an IMA frame. The Frame status
bits are cleared by writing 0 to the bit. The Ready bit is set to 1 when the transfer is complete. Bit 6 is a latched bit
in the IRQ Link 0 Status (0x0435) register and is cleared by overwriting it with 0.
Each of these two interrupt sources can be masked by writing a ’1’ to the bit corresponding to the interrupt source in
the IRQ Link 0 Enable (0x0445) register.
6.2.3
The IRQ Link TC Overflow Status Registers (0x0410 - 0x041F) report the overflow condition from any of the
counters associated with the TX TDM link, the RX TDM link or the TX UTOPIA I/F. They also report the overflow
condition from the level of the UTOPIA RX FIFO when the link is used in TC mode. The 13 interrupt sources are
organized as follows:
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6.2.4
The sources of IMA Group overflow conditions are organized in two levels of registers:
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The IRQ IMA Group Overflow Status (0x0457) register indicates which one of the eight IMA Groups is reporting
the ICP cell internal transfer is complete (reported by any IMA Group TX ICP Cell Ready bit)
the end of an IMA frame on the reference link of an IMA Group
1 bit (12) for the RX UTOPIA FIFO for TC mode overflow
4 bits (11:8) for the UTOPIA Input Counters
4 bits (7:4) for the TX TDM Link Counters
4 bits (3:0) for the RX TDM Link counters
eight low level, 5-bit registers (one register per IMA Group)
one intermediate 4-bit register that is used to report the overflow conditions for each IMA Group to minimize
the number of accesses when identifying the source of an overflow condition
IRQ Link TC Overflow Status Registers
IRQ IMA Group Overflow Status and Enable Registers
Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers
Zarlink Semiconductor Inc.
MT90222/3/4
70
Data Sheet