MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet
MT90880B
Related parts for MT90880B
MT90880B Summary of contents
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... WAN Access Interface Local TDM Interface e.g. for connection to local resource pool Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT90880B/IG/BP1N MT90881A/IG/BP1N MT90882B/IG/BP1N MT90883A/IG/BP1N Applications • Packet backplane interconnection • ...
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Description The MT9088x is a family of highly functional TDM to Packet bridging devices. It provides a bridge between a WAN environment based on constant bit rate TDM streams and a packet domain based on Ethernet technology capable ...
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The following external documents and standards are referenced in this data sheet: Title 1. Local and Metropolitan Area Networks, Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifi- cations 2. PCI Local Bus ...
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Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operation of the WAN Receive Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Packet Interface ...
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Figure 1 - MT90880 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49 - External RAM Single Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Variant Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the November 2004 issue. Page Item 17 Table 8 71 “Open Drain Circuitry“ The following table captures the changes from the June 2004 issue. Page Item 81 “DC Characteristics“ Table ...
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Physical Specification The device is contained in a 456-ball plastic ball grid array (456 PBGA) package: • Body Size • Ball Count: 456 • Ball Pitch: 1.0 mm • Ball Matrix ...
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External Interface Description The following key applies to all tables: O Output I Input D internal 100 KΩ pull-down resistor present U internal 100 KΩ pull-up resistor present 3.1 WAN Access Interface All WAN Access Interface signals are 5 ...
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Signal I/O WAN_CLKI[23: J23 [23], J24 [22], H22 [21], G22 [20], E26 [19], E24 [18], A26 [17], A24 [16], A23 [15], E19 [14], B21 [13], B20 [12], A20 [11], B18 [10], C17 [9], C16 [8], D15 [7], A15 ...
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Signal I/O LOC_STO [7: [7], L4 [6], K2 [5], L3 [4], L2 [3], P4 [2], M2 [1], N3 [0] c4ob O B8 fp4ob O C8 c8ob O A7 fp8ob O A6 c16ob O B7 fp16ob O D8 ode ...
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Signal I/O m0_txclk I U AB9 m0_rxd[3: AF8 [3], AE8 [2], AE9 [1], AD9 [0] m0_rxdv I D AF7 m0_rxclk I U AB10 m0_rxer I D AD8 m0_crs I D AC9 m0_col I D AE7 MII Port B ...
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Signal I/O ref_clk I U AB11 RMII Port A rm0_rxd[1: AE9 [1], AD9 [0] rm0_rxdv/ crs I D AF7 rm0_txen O U AD6 rm0_txd[1: AE6 [1], AD7 [0] RMII Port B rm1_rxd[1: AE13 [1], ...
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Signal I/O pci_trdy AA23 pci_irdy AF26 pci_stop AC24 pci_devsel AE26 pci_idsel I AB20 pci_perr AD26 pci_serr AB24 pci_lock Y22 pci_inta AF19 PCI_M66EN I O ...
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System Control Interface The system signals are 5 V tolerant. RESOUT# is low while S_RST# is low. The core of the chip will be held in reset for 16348 S_CLK cycles after S_RST# has gone high and 16348 PCI_CLK ...
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Signal I/O iddq I AD23 sclk_AT1 O B26 pclk_AT1 O AF24 ram_clk O Y2 3.7.3 Test Operating Modes 1) Normal operating mode (T_MODE[1:0] = '11') The device samples the T_D pins to determine the required operating mode shortly after reset ...
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Board level continuity test mode (T_MODE[1:0] = '10') In continuity test mode the core of the chip is held in reset. Pin T_D[10] selects the board level test mode. 3) Scan test mode (T_MODE[1:0] = '01') System clock and ...
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Line Input Card MT9076 Framer Line Input Card MT9076 Framer PSTN Line Input Card MT9076 Framer Line Input Card MT9076 Framer Figure 2 - Multiservice Access Platform using the MT90880 4.2 Circuit Emulation Services The MT9088x family can be used ...
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Line Input Card T1/E1/ MT90880 ISDN MT9076 TDM-IP Framer/LIU Processor Circuit Emulation Interworking Function Figure 3 - Circuit Emulation Services over the packet network 4.3 Internet Off-load Internet off-load is a means of relieving the congestion in circuit-switching equipment caused ...
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Remote Access Concentration In a similar manner to the internet off-load solution outlined above, the MT9088x devices can also be used to route traffic to a remote resource pool. This allows resources to be centralized, with multiple line cards ...
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Local Resource Pool Example For smaller systems, the built-in TDM switch allows traffic to be switched out to a local resource pool on the line card. The provision of a high bandwidth, 33 MHz PCI interface allows the processed ...
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H.100/H.110 Extension The H.100/H.110 TDM bus commonly used in today’s computer telephony systems is based on a physical backplane the width of a single telecom rack. Extending the reach of the bus is expensive using traditional TDM infrastructure. Such ...
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H.100/H.110 bus segment MT90866 MT90880 H.110 TDM-IP Switch Processor Figure 8 - H.100/H.110 Expansion using Ethernet Switching Fabric 5.0 Functional Operation 5.1 Overview The MT9088x family provides the data-plane processing to enable constant bit rate TDM services to be carried ...
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TDM equipment constant bit rate TDM link The MT9088x family provides structured, synchronous TDM service, operating at the 64 Kbs channel (DS0) level. The devices exhibit the following general service characteristics × 64 Kbs trunking of any group ...
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Basic Operation A diagram of the MT90880 device is given in Figure 10, which shows the major data and control flows between functional components. Local TDM Interface 32 ports Mbit/s 1K Switch WAN Interface ...
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Trunking is not limited to contiguous timeslots. Each context is capable of carrying any combination of timeslots, taken from any stream. However, packets are assembled sequentially, with data placed into the packet as it arrives, maintaining timeslot and stream order. ...
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Once confirmation has been received, the changes are activated at the transmit end. A synchronization flag in the header marks the first modified packet. This tells the receiver to switch over to the amended context information. Removal of a ...
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Packet Interface to WAN Access Interface Incoming data is received by the MAC, and its destination address is checked. Packets intended for this device are passed to the packet receive block for placing in external memory, while the header is ...
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WAN Access Interface to Packet Interface via a Local Resource Pool Data traffic received on the WAN interface is diverted to the TDM switch and out of the local TDM interface for processing in a local resource pool (e.g., a ...
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Figure 14 - Packet to WAN Data Flow via Local Resource PCI Interface to Packet Interface The host CPU or other devices can use the MT9088x device to send data via the packet network. The data to be sent is ...
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Packet Interface to PCI Interface Similarly, packets destined for the host CPU or other PCI devices can be sent over the packet network to the PCI device. The headers of incoming packets are parsed by the Packet Classifier, and can ...
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Stream 0 Channel 0 Stream 1 Channel 0 Stream 2 Channel 0 Stream 31 Channel 0 Figure 17 - Channel and stream order for packet formation Each packet contains one or more complete TDM frames of data, in sequential order. ...
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Fixed Header Data for TDM Frame 1 Data for TDM Frame 2 Data for TDM Frame n Figure 18 - Packet Structure for MT9088x Family 5.4.3 Context Descriptor Protocol The MT9088x family uses a two-byte field within the packet header ...
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The remote end is signalled to expect a modified context, and its host sets up the new context information. This new setup is activated on receipt of the first packet containing the ...
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Context Modification (Addition or deletion of physical channels) Context modification must be an atomic operation. Therefore, if the host modifies the context setup, it must wait until that change has been carried out before attempting further modifications. This will ...
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Context Removal Context removal is required when all active channels are removed from a context. Normally, channel deletion is signalled in the first packet of the modified context. However, when the last channel is deleted from a context, no ...
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Functional Block Descriptions 6.1 WAN Interface and Multiplexers The WAN Interface provides the synchronization between the external TDM streams and the internal logic. It also multiplexes the between the cross-connect switch and two TDM processing blocks. The multiplexing allows ...
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Operational Modes The WAN Interface operates in three distinct modes: synchronous master , synchronous slave and asynchronous mode. Synchronous Master Mode In synchronous master mode , the MT9088x supplies the clock and frame signals to the external WAN infrastructure ...
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MT9076 DO Combined DI Framer-LIU line RxFP C4b F0b MT9076 DO Combined DI Framer-LIU line RxFP C4b F0b MT9076 DO Combined DI Framer-LIU line RxFP C4b F0b Figure 20 - Connecting ...
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The MT9088x family can also be connected as slave devices to older TDM backplanes such as MVIP and H-MVIP buses (reference 9), either directly or through a TDM switch. In synchronous slave mode although the DPLL is ...
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Asynchronous Mode In asynchronous mode , each port uses its own clock to sample and drive the data streams. Since each clock can slightly different frequency, trunking of timeslots is restricted to be within the same stream. ...
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TDM Cross-Connect Switch The TDM switch is a non-blocking switch with 1024 bi-directional channels. It can be used both for routing WAN traffic out to the local TDM interface, and for re-ordering timeslots on the way in or out ...
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Per-channel high impedance output control for local and WAN streams • Per-channel message mode for local and WAN output streams • PRBS pattern generation and testing • Block memory programming for fast device initialisation • Channel duplication facility for ...
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Use of a separate context may not be acceptable, since the number of contexts on the MT9088x family is limited to 128. Therefore the only option is to use the switch to re-order the channels. As described above ...
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Programmable size jitter buffer size 6.4 Operation of the WAN Receive Block The diagram in Figure 24 shows a simplified, conceptual diagram of the WAN Receive Controller, demonstrating the principles of its operation. circulating context timeslot lookup pointer table ...
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Context Look-Up Table field definitions Context ID The identity of the context that the channel is a member of. Value is in the range 0-127. V Valid Channel bit. A '1' indicates that the channel is an active member ...
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WAN Transmit Controller is updated and ready to receive the modified packets prior to applying the changes to the local WAN Receiver. To add new channels to an existing context, the context lookup table is programmed ...
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Jitter Buffer Underrun The jitter buffer will "underrun", i.e. empty completely under the following circumstances: • If the TDM data is played out of the TDM interfaces faster than the original TDM interface • If the packet delay variation in ...
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The maximum size of the jitter buffer is governed by the drop threshold described above. When the drop threshold is reached, any further packets arriving are discarded until the buffer depth has reduced by being played out of the TDM ...
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Options Class 3 Option 1 (default) SP Option 2 SP Option 3 SP Option 4 WFQ Table 19 - Configuration of Packet Queues Queues defined as strict priority take precedence over queues designated as using weighted fair queuing. Hence, in ...
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In the absence of a priority requirement, the weights should be set to the same value to allow equal access to the bandwidth. For example, in option 4 all the weights should be set to 16, allocating 25 Mbs per ...
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Drop Thresholds The context queues are used to buffer the constant bit rate TDM interfaces from the variable delays experienced in the packet network (see the section on "Jitter buffer Operation", on page 28). The initial size of this jitter ...
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Where packets have to sent across a routed network, rather than a simple switched Ethernet, IP can be used to provide the network layer. CDP can sit directly on top of the IP layer, but in this case a protocol ...
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RFC 1213 MIB II. • RFC 1757Remote Network Monitoring MIB (for SMIv1) • RFC 2819Remote Network Monitoring MIB (for SMIv2) • RFC 2863Interfaces Group MIB 6.8 Packet Classification This is used to determine the destination of incoming traffic on ...
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Header Mask Stage Masked Header Comparison Stage Comparator Comparison result 1 Look-up Stage Once a successful match is established, the characteristics of each traffic class may be determined by a look-up process. If the matched class contains TDM traffic, the ...
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Unmatched traffic is also forwarded to the CPU using queue 0. This allows the CPU to analyse the traffic to work out what should be done with it. Alternatively, if the drop threshold on queue 0 is set very small, ...
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Fields from Packet Engine Control Register: Control Register Field CPU_SEL1 CPU_PRI1 Byte offset to Context Descriptor Table 22 - Control Register Fields for Example Traffic Class 1 Traffic Class 2: Ethernet - IPv4 - UDP - CDP Configure the mask ...
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Protocol Field Checksum Mask Context Descriptor Version Allow match Context Switch Mask Context ID[11:7] Allow match Context ID[6:0] Mask Remainder of the header Mask Table 23 - Pattern Matching for Example Traffic Class 2 (continued) Fields from Packet Engine Control ...
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Protocol Field Flags Mask Fragment Offset Mask Time to Live (TTL) Mask Protocol Mask Header Checksum Mask Source IP address Mask Destination IP address Allow Match Remainder of the header Mask Table 25 - Pattern Matching for Example Traffic Class ...
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Protocol Field Identification Mask Flags Mask Fragment Offset Mask Time to Live (TTL) Mask Protocol Allow Match Header Checksum Mask Source IP address Mask Destination IP address Allow Match Remainder of the header Mask Table 27 - Pattern Matching for ...
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External Memory Requirements The majority of the memory is used by the jitter buffer, which compensates for delay variation (PDV) in the packet network. The amount of memory required to compensate for a given PDV depends on the mean ...
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MT9088x can connect four external memory devices, with a total capacity Mbytes. Connecting to a single external memory devices The diagram in Figure 28 shows how to connect the MT90880 ...
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Connecting to multiple external memory devices The four devices are connected in banks, and the MT90880 device automatically switches to the next bank when the address exceeds the range of the bank. Therefore the MT90880 needs to be informed during ...
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MT9088x device S_CLK RAM_A[19:4] RAM_A[3] RAM_A[2] RAM_ADSC# RAM_WE[0]# RAM_WE[1]# RAM_WE[2]# RAM_WE[3]# RAM_OE[0]# RAM_OE[1]# RAM_OE[2]# RAM_OE[3]# RAM_D[7:0] RAM_D[15:8] RAM_D[23:16] RAM_D[31:24] Figure 29 - Connecting the MT90880 to Multiple External Memory Devices 6.9.4 External Memory Interface Timing The timings for the external ...
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Maximum allowable clock skew This time must be reduced by transmission times of signals across the board between the MT90880 and the memory, e.g. RAM_WE[x]# and the data bus practice, the clock skew must be somewhat lower than ...
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Target Transaction Support Supported Transactions The MT9088x family supports the following PCI target transactions: • Memory read (single cycle only) • Memory write (single cycle only) • Configuration read • Configuration write Burst Transactions Burst transactions are not supported ...
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The PCI configuration registers are used to set up how the MT9088x will fit into the system in which it will be placed. They support the method defined in the PCI Rev 2.2 Specification to determine the size of the ...
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Open Drain Circuitry The MT9088x signals pci_serr# and pci_inta# do not behave as open drain. Signals pci_serr# and pci_inta# should behave as open drain. The following external circuitry should be used, so that the board on which the MT9088x ...
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DMA Descriptor Rings and Lists Data for transfer to and from the MT90880 is held in a Descriptor Ring or List data structure in system memory (see Figure 33 and Figure 34). Once the CPU has set up the ...
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Head Descriptor Link Command Buffer Pointer Status Data Buffer Full details of the DMA descriptor data structures, and the fields within the descriptor, are provided in the "MT90880 Programmers' Model " (related document 1). 6.11.2 Data Transfer from CPU to ...
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MT90880 Packet Classification Search the incoming packets for a match and forward to the appropriate queue Figure 35 - DMA Operation from CPU Packet Queues Queue Priority While the CPU queues have no inherent priority levels associated with them, in ...
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Test Access Port (TAP) The Test Access Port (TAP) accesses the MT9088x test functions. It consists of four input pins and one output pin as follows: Test Clock Input (TCK) TCK provides the clock for the test logic. The ...
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DPLL Specification The MT9088x contains an internal Digital Phase Locked Loop (DPLL) which exceeds the requirements of Stratum 4E. This is provided both to synchronise to external references and generate the internal clocks required by the device when operating ...
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Two factors affect the frequency stability while in Holdover. The first factor is the drift on the master clock (S_CLK) frequency. Any drift in master clock frequency translates directly into drift on the holdover frequency. Note that the absolute master ...
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Figure 37 - Detailed DPLL Jitter Transfer Function Diagram All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Using the method mentioned above, the jitter attenuation can be calculated for all combinations of inputs ...
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Free-run Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. 6.13.4 DPLL Performance Parameters Table 30 lists the key performance parameters of the DPLL. Parameter Intrinsic jitter Lock ...
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Recommendation This device should not be used in a half-duplex network application. The final link to the device should be as short as possible, (for example from an Ethernet Switch), in order to minimise the probability of corrupted packets ...
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Recommended Operating Conditions - Characteristics Operating Temperature Junction temperature Package thermal resistance to ambient Positive Supply Voltage, I/O Positive Supply Voltage, Core Positive Supply Voltage, Core Input Voltage Low - all inputs Input Voltage High Input Voltage High ...
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Input Levels Characteristics Input Low Voltage Input High Voltage Positive Schmitt Threshold Negative Schmitt Threshold 9.0.2 Output Levels Characteristics Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Current Output High Current Output Low ...
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AC Characteristics 10.1 WAN Access Interface 10.1.1 Slave Clock Mode Data format ST-bus 8.192 Mbs mode WAN_CLKI frequency WAN_CLKI High Width WAN_CLKI Low Width ST-bus 2.048 Mbs mode WAN_CLKI frequency WAN_CLKI High Width WAN_CLKI Low Width Generic E1 2.048 ...
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Channel 31 bit 0 WAN_CLKI WAN_FRMI WAN_STI tSTOD WAN_STO Channel 31 bit 0 Figure 39 - WAN Bus Slave Mode Timing at 2.048 Mbs Generic E1 Mode Channel 127 bit 1 WAN_CKLI WAN_FRMI tSTIS WAN_STI WAN_STO Channel 127 bit 1 ...
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Clock Master Mode Data format ST-bus 8.192 Mbs mode WAN_CLKO frequency WAN_CLKO High Width WAN_CLKO Low Width ST-bus 2.048 Mbs mode WAN_CLKO frequency WAN_CLKO High Width WAN_CLKO Low Width Generic E1 2.048 Mbs WAN_CLKO frequency mode WAN_CLKO High Width ...
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Channel 31 Bit 0 WAN_CLKO WAN_FRMO WAN_STI tSTOD WAN_STO Ch 31 Bit 0 Figure 42 - WAN Bus Clock Master Mode at 2.048 Mbs - Generic E1 Mode Channel 31 Bit 0 WAN_CLKO WAN_FRMO WAN_STI tSTOD WAN_STO Ch 31 Bit ...
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Clock C4OB High Width Clock C4OB Low Width C*OB to FP*OB delay WAN_STO Delay LOC_STI Setup Time LOC_STI Hold Time Table 33 - Local TDM Interface Timing (continued) Channel 31 Bit 0 C4OB FP4OB LOC_STI LOC_STO Ch 31 Bit 0 ...
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Channel 127 Bit 0 C16OB FP16OB LOC_STI LOC_STO Ch 127 Bit 0 10.3 Packet Interface 10.3.1 MII Transmit Data for the MII packet switching is based on Specification IEEE Std 802.3u – 1995. Parameter TXCLK period TXCLK high time TXCLK ...
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TXCLK tEV TXEN tDV TXD Figure 47 - MII Port Transmit Characteristics 10.3.2 MII Receive Parameter Data input setup time Data input hold time Data valid input setup time Data valid input hold time RXCLK high wide time RXCLK low ...
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RMII Interface Parameter Clock Frequency Clock Duty Cycle Setup Time to Clock Rising Edge RXD[1:0], CRS_DV Hold Time from Clock Rising Edge RXD[1:0], CRS_DV TXD[1:0] TX_EN Output delay Table 36 - Packet Interface Timing - RMII Interface 10.4 External ...
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SCLK Trav RAM_A Trav RAM_ADSC RAM_RW RAM_OE RAM_D Figure 49 - External RAM Single Cycle Read 1 2 S_CLK Trav RAM_A A1 Trav RAM_ADSC RAM_OE Trav RAM_RW RAM_D Figure 50 - External RAM Multi Cycle Read MT90880/1/2/3 3 ...
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S_CLK Trav RAM_A Trav RAM_ADSC Trav RAM_RW RAM_OE Trdv RAM_D Figure 51 - External RAM Single Cycle Write 1 2 S_CLK Trav RAM_A Trav RAM_ADSC Trav RAM_RW RAM_OE Trdv RAM_D Figure 52 - External RAM Multi Cycle Write ...
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System Control Port Parameter System Clock Frequency System Clock Accuracy (synchronous mode) System Clock Accuracy (asynchronous mode) Note 1: The System clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for short durations ...
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MT90880/1/2/3 JTAG Clock Timing t RST TRST Figure 53 - JTAG Clock and Reset Timing 94 Zarlink Semiconductor Inc Low HIGH t CYC t RSTSU Data Sheet ...
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Glossary ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDP Context Descriptor Protocol (used to indicate the contents of a packet stream or "context") CES Circuit Emulation Services DBCES Dynamic Bandwidth Circuit Emulation Services DMA Direct Memory Access DPLL ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...