MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 29

• Manufacturer Part Number: MT90880B
• Description: TDM to Packet Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Trunking is not limited to contiguous timeslots. Each context is capable of carrying any combination of timeslots,
taken from any stream. However, packets are assembled sequentially, with data placed into the packet as it
arrives, maintaining timeslot and stream order.
5.2.2
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. For example, to keep the
latency of the TDM traffic low, TDM contexts can be prioritized over traffic from the CPU. Similarly, context
control traffic can in turn be prioritized over maintenance traffic. Two types of prioritization are allowed:
weighted fair queuing , where a traffic class is allocated a fixed proportion of the bandwidth, and strict priority ,
where all higher priority traffic is sent before any lower priority traffic.
On transmission, the Packet Transmitter appends a packet header, which has been set up in advance by the
control processor. This allows the higher level protocols to be user-defined. The header is entirely user
programmable, allowing any protocol to be used provided that the field contents remain static (i.e. do not
change from packet to packet). Supported protocols include Ethernet, VLAN, IPv4, UDP (without using the
checksum) and CDP (Zarlink's “Context Descriptor Protocol” on page 36 ).
5.2.3
The control processor can generate packets directly, allowing it to use the network for out-of-band
communications. This can be used for out-of-band transmission of control data or network setup information,
e.g., routing information. The PCI interface can also be used by a local resource for network transmission of
processed data. Each of these types of traffic can be allocated a different class of service, allowing the
bandwidth of the link to be carefully managed.
A DMA controller is built into the PCI interface to allow pre-formatted packets to be read directly from PCI
memory and queued to the appropriate packet interface.
5.2.4
Incoming data traffic on the packet interface is received by the MACs, which determines if the packets are
intended for the device. If they are, the packets are forwarded to a packet classifier to determine the destination.
This can either be the TDM domain (either WAN or Local interfaces) or the PCI interface. WAN traffic is then
further classified to determine the context it is intended for.
Each TDM context has an individual queue, and the TDM re-formatting process re-creates the TDM streams
from the incoming packet streams. Upon context setup, the TDM output is delayed by a programmable number
of TDM frames, creating a jitter buffer. This is required to smooth out the variation in delay between individual
packets.
There are four separate queues to the PCI interface, allowing different traffic flows to be classified separately.
For instance control information could be directed to one queue, with traffic for a local resource pool directed to
another queue. This simplifies access to the device by multiple resources or applications. Again the DMA
controller can be used to retrieve packet data and write it out into external system memory on the PCI bus.
5.2.5
Context setup must be negotiated between transmitting and receiving devices. This is handled by out-of-band
signalling between the control processors at each end. Once the context has been established, the first data
packet is transmitted. Each data packet contains a field in the header identifying the context to which it applies.
This allows the receiving end to decode the packet and forward the data to the correct TDM channels.
Context modification (e.g., addition or deletion of timeslots) must also be set up in advance before the actual
modification takes place. Changes are signalled out of band by the transmit end, which waits for confirmation
from the receive end. This indicates that the amendments have been made, and it is ready to handle modified
Packet Transmission
CPU Packet Generation
Packet Reception
Call Setup and Control
Zarlink Semiconductor Inc.
MT90880/1/2/3
29
Data Sheet