MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 90

• Manufacturer Part Number: MT90880B
• Description: TDM to Packet Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.3.3
10.4
Clock Frequency
Clock Duty Cycle
Setup Time to Clock Rising Edge
RXD[1:0], CRS_DV
Hold Time from Clock Rising Edge
RXD[1:0], CRS_DV
TXD[1:0] TX_EN Output delay
S_CLK to Data Out Valid Delay
(RAM_D)
S_CLK to Signal Valid Delay
(RAM_A, RAM_ADSC#, RAM_RW,
RAM_OE)
RAM_D setup time before S_CLK
rising edge
RAM_D hold time after S_CLK
rising
External Memory Interface
RMII Interface
Parameter
Parameter
Table 36 - Packet Interface Timing - RMII Interface
Table 37 - External Memory Timing
Symbol
Symbol
T
T
T
T
t
t
RDV
RDS
RDH
t
DV
RAV
S
H
Zarlink Semiconductor Inc.
MT90880/1/2/3
Min.
Min.
35
4
2
3
0
90
Typ.
Typ.
50
Max.
Max.
65
14
7.5
10
Units
MHz
Units
ns
ns
ns
%
ns
ns
ns
ns
± 50 ppm
Notes
Notes
Data Sheet