MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 69

• Manufacturer Part Number: MT90880B
• Description: TDM to Packet Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.10.2
Supported Transactions
The MT9088x family supports the following PCI target transactions:
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Burst Transactions
Burst transactions are not supported by the MT9088x. The device will respond with a Target Disconnect cycle if
a burst access is attempted.
Timeout on Target Read
A PCI Read access timeout is available, set to 32 system clock cycles (485 ns). A timeout will not generate an
interrupt or an error, but will result in the data read being 0xFFFFFFFF. The timeout can be disabled.
Fast Back to Back cycles
The MT9088x is capable of receiving fast back to back cycles as a PCI Target device.
PCI Error, Abort and Re-try sources
The following events are among those that will cause a PCI error or abort or re-try event to occur.
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6.10.3
The MT9088x becomes a PCI Master whenever DMA accesses are invoked to transfer packets from the
external packet memory to the Host CPU or vice versa using the DMA controller. One PCI Bus request output
and one PCI Bus grant input is provided to allow the MT90880 to request and be granted the PCI bus.
The MT90880 does not generate Fast Back to Back cycles when in Master mode.
Transaction Timeout counters
When the MT9088x is a Master on the PCI bus, two counters are provided to allow the system to recover in the
event of the PCI Target behaving abnormally:
The TRDY timeout counter is programmable, and holds the number of cycles the Master will wait before
abandoning the cycle. Reasons for timing out include the absence of the TRDY or Stop signals to terminate the
cycle normally. This timeout can be disabled.
The Retry timeout counter allows the user to limit the number of re-try cycles that the MT90880 as PCI Master
will attempt before abandoning the cycle. This timeout can be disabled.
6.10.4
The MT9088x is configured as a PCI Satellite device. Therefore the PCI interface must be configured by the
Host PCI device connected to the bus before the internal register and memory space can be accessed by the
Host. This is achieved by programming the device PCI configuration registers.
Memory read (single cycle only)
Memory write (single cycle only)
Configuration read
Configuration write
Address Parity error: A Target cycle to the MT9088x with an Address Parity error will cause a PCI System
Error to be generated.
Data Parity error: A Target write cycle to the MT9088x with a Data Parity error will cause a PCI Parity Error
to be generated.
Target Transaction Support
Master Support
Configuration and Registers
Zarlink Semiconductor Inc.
MT90880/1/2/3
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Data Sheet