MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 88

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MT90880B

Manufacturer Part Number
MT90880B
Description
TDM to Packet Processors
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
10.3
10.3.1
Data for the MII packet switching is based on Specification IEEE Std 802.3u – 1995.
TXCLK period
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
TXCLK rise to TXD active delay
TXCLK to TXEN active delay
LOC_STO
Packet Interface
LOC_STI
FP16OB
MII Transmit
C16OB
Parameter
Channel 127 Bit 0
Ch 127 Bit 0
Table 34 - Packet Interface Timing - MII Transmit
Figure 46 - Local Bus Timing at 8.192 Mbs
tSTIS
tFOD
tSTIH
Symbol
t
t
t
t
CLO
t
t
t
CHI
CC
CR
CF
DV
EV
Zarlink Semiconductor Inc.
MT90880/1/2/3
tC16L
tC16L
tSTOD
Min.
140
140
0
0
-
-
-
tC16H
tC16H
88
Channel 0 Bit 7
tFOD
10 Mbs
Typ.
Ch 0 Bit 7
400
-
-
-
-
-
-
Max.
260
260
25
25
5
5
-
tSTIS
tSTIH
Min.
14
14
0
0
-
-
-
tSTOD
100 Mbs
Typ.
Channel 0 Bit 6
40
-
-
-
-
-
-
Ch 0 Bit 6
Max.
26
26
25
25
5
5
-
Data Sheet
Units
ns
ns
ns
ns
ns
ns
ns

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