MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 42

• Manufacturer Part Number: MT90880B
• Description: TDM to Packet Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The MT90880 may also be used as a TDM backplane master, such as an H.100/H.110 bus (reference 8), or an
H-MVIP backplane (reference 9). The integrated DPLL provides a very stable, low jitter timing reference
suitable for use as the master timing source for a backplane, with automatic, low MTIE failover from primary to
secondary reference in the event of a reference failure.
Synchronous Slave Mode
In synchronous slave mode , the MT9088x accepts a clock from the WAN, rather than mastering the clock. One
of the 32 incoming ports is chosen to provide the primary timing reference, and its clock and frame pulse are
used directly to clock the data in and out on all 32 streams, bypassing the DPLL output. Again, a secondary
reference port may be chosen, and this is automatically switched in if the primary fails. Unused clock and frame
inputs may be left unconnected, as all inputs are connected to an internal 100 K Ω pull-down resistor to prevent
them from floating.
A typical application for this configuration is to connect to a TDM backplane, where the MT9088x is used as a
backplane slave device. An example of this is Figure 21, which shows an MT90880 connected as a backplane
slave to an H.100/H.110 TDM backplane (reference 8). An MT90866 TDM switch device is shown interfacing
the MT90880 to the backplane. Up to three MT90880 devices could be connected directly to a single MT90866
switch. The CT_C8_A and CT_C8_B backplane clocks are used as the primary and secondary master clocks to
T1 or E1 line
T1 or E1 line
T1 or E1 line
Framer-LIU
Framer-LIU
Framer-LIU
Combined
Combined
Combined
MT9076
MT9076
MT9076
Figure 20 - Connecting to Framers in Synchronous Master Mode
RxFP
RxFP
RxFP
C4b
C4b
C4b
F0b
F0b
F0b
DO
DO
DO
DI
DI
DI
8 KHz
8 KHz
8 KHz
4.096 MHz
8 KHz
Zarlink Semiconductor Inc.
MT90880/1/2/3
WAN_STI0
WAN_STO0
WAN_CLKI0
WAN_FRMI0
WAN_STI1
WAN_STO1
WAN_CLKI1
WAN_FRMI1
WAN_STI31
WAN_STO31
WAN_CLKI31
WAN_FRMI31
WAN_CLKO
WAN_FRMO
42
ST-Bus 2.048Mbit/s mode
Master Clock Output
TDM-IP Processor
DPLL
MUX
MT90880
TDM clock and frame
internally used
Data Sheet