MT90880B ZARLINK [Zarlink Semiconductor Inc], MT90880B Datasheet - Page 83

• Manufacturer Part Number: MT90880B
• Description: TDM to Packet Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.0
10.1
10.1.1
Note 1:
ST-bus 8.192 Mbs mode
ST-bus 2.048 Mbs mode
Generic E1 2.048 Mbs
mode
All modes
WAN_FRMI
WAN_CLKI
WAN Access Interface
Data format
asynchronous mode, the clock may be any frequency, provided there are 32 clocks between frame pulses (128 in 8.192 Mbs
mode)
In synchronous mode the clock must be within the locking range of the DPLL to function correctly ( ± 245 ppm). In
WAN_STO
AC Characteristics
WAN_STI
Slave Clock Mode
Channel 31 Bit 0
Table 31 - WAN Access Interface Timing - Slave Mode
Ch 31 Bit 0
Figure 38 - WAN Bus Slave Mode Timing at 2.048 Mbs
WAN_CLKI frequency
WAN_CLKI High Width
WAN_CLKI Low Width
WAN_CLKI frequency
WAN_CLKI High Width
WAN_CLKI Low Width
WAN_CLKI frequency
WAN_CLKI High Width
WAN_CLKI Low Width
WAN_FRMI Setup Time
WAN_FRMI Hold Time
WAN_STO Delay
WAN_STI Setup Time
WAN_STI Hold Time
B0
Parameter
tSTIS
tSTIH
tFOIS
Zarlink Semiconductor Inc.
MT90880/1/2/3
tC4L
tC4L
tSTOD
tFOIH
83
Channel 0 Bit 7
tC4H
tC4H
Symbol
t
t
f
t
t
t
t
t
f
t
f
t
STOD
C16P
C16H
t
t
C16L
FOIS
FOIH
STIS
STIH
Ch 0 Bit 7
C4H
C2H
C4P
C2P
C4L
C2L
Min.
B7
5
5
1
5
5
tSTIS
tSTIH
16.384
4.096
2.048
Typ.
122
122
244
244
30
30
tSTOD
Channel 0 Bit 6
Max.
20
Ch 0 Bit 6
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
Note 1
Note 1
Note 1
Notes